特性
- Low-Power HCSL outputs with Zo = 85Ω; save power and board space - no termination resistors required. Ideal for blade servers
- Space-saving 40-pin VFQFPN package
- Fixed feedback path for 0ps input-to-output delay
- 6 OE# pins; hardware control of each output
- PLL or bypass mode; PLL can de-jitter incoming clock
- Selectable PLL bandwidth; minimizes jitter peaking in downstream PLLs
- Spread spectrum compatible; tracks spreading input clock for low EMI
- Cycle-to-Cycle jitter < 50ps
- Output-to-Output skew < 65ps
- Input-to-Output delay variation < 50ps
- PCIe Gen 3 phase jitter < 1.0ps RMS
- QPI/UPI 9.6GT/s 12UI phase jitter < 0.2ps RMS
描述
The 9ZXL0651 is a low-power 6-output differential buffer that meets all the performance requirements of the Intel DB1200Z specification. It consumes 50% less power than standard HCSL devices and has internal terminations to allow direct connection to 85Ω transmission lines. It is suitable for PCI Express Gen 1/2/3 or QPI/UPI applications and uses a fixed external feedback to maintain low drift for demanding QPI/UPI applications.
产品参数
| 属性 | 值 |
|---|---|
| Temp. Range (°C) | 0 to 70°C |
封装选项
| Pkg. Type | Pkg. Dimensions (mm) | Lead Count (#) | Pitch (mm) |
|---|---|---|---|
| VFQFPN | 5.0 x 5.0 x 0.9 | 40 | 0.4 |
应用
- Buffer for Romley, Grantley and Purley Servers, SSDs, and PCIe
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A detailed overview of IDT's full-featured PCI Express (PCIe) clock and timing solutions. The presentation addresses PCIe Gen 1, Gen 2, Gen 3, and Gen 4 architectures and how IDT's industry-leading solutions provide all the functions, features, and performance required by the application.
Presented by Ron Wade, System Architect at IDT. For more information visit the PCIe clocks page.