瑞萨电子 (Renesas Electronics Corporation)
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9ZXL1252E

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12-Output DB1200ZL PCIe Clock Clock Buffer with SMBus Write Protection

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特性

  • SMBus Write Lock feature; increases system security
  • PCIe Gen 1–5 compliance
  • LP-HCSL outputs with 85Ω Zout; eliminate 48 resistors, save 82mm² of area
  • 12 OE# pins; hardware control of each output
  • 9 selectable SMBus addresses; multiple devices can share the same SMBus segment
  • Selectable PLL BW; minimizes jitter peaking in cascaded PLL topologies
  • Hardware/SMBus control of PLL bandwidth and bypass; change mode without power cycle
  • Spread spectrum compatible; tracks spreading input clock for EMI reduction
  • 100MHz and 133.33MHz PLL mode; UPI and legacy QPI support
  • 9mm x 9mm 64-QFN package; small board footprint
查找应用特定型时钟的其他产品
9ZXL06x2E-08xxE-12x2E - Block Diagram
9ZXL1252E - Pinout
9ZXL06x2E-08xxE-12x2E - Block Diagram
9ZXL1252E - Pinout

描述

The 9ZXL1252E is a second-generation, enhanced-performance DB1200ZL differential buffer. The part is a pin-compatible upgrade to the 9ZLX1252A while offering a much-improved phase jitter performance and an SMBus Write Lock feature for increased system security. A fixed external feedback maintains low drift for critical QPI/UPI applications. The 9ZXL1252E has an SMBus Write Lockout pin for increased device and system security.

产品参数

属性值
Diff. Outputs12
Diff. Output SignalingLP-HCSL
Output Freq Range (MHz)1 - 400
Diff. Inputs1
Diff. Input SignalingHCSL
Accepts Spread Spec InputYes
Power Consumption Typ (mW)481
Supply Voltage (V)3.3 - 3.3
Output TypeLP-HCSL
Diff. Termination Resistors24
Package Area (mm²)81
Battery BackupNo
Battery SealNo
CPU Supervisory Function PORNo
Crystal Frequency TrimmingNo
Frequency Out PinNo
Inputs (#)1
Input Freq (MHz)33 - 150
FunctionZero Delay Buffer
Input TypeHCSL
Output Banks (#)1
Core Voltage (V)3.3
Output Voltage (V)0.7

封装选项

Pkg. TypePkg. Dimensions (mm)Lead Count (#)Pitch (mm)
VFQFPN9.0 x 9.0 x 0.9640.5

应用

  • Servers/High-performance computing
  • nVME storage
  • Networking
  • Accelerators
  • Industrial control

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Introducing Renesas’ enhanced PCIe clock buffer family. These PCIe Gen5 clock buffers offer fanout and zero-delay operating modes, supporting both legacy systems and the most complex timing trees within a single device. Unlike many existing solutions, whose performance limitations force their use in fanout buffer mode, these clock buffers meet both PCIe Gen5 and prominent CPU-specific phase jitter requirements in all operating modes. The extremely low 50fs rms PCIe Gen5 additive phase jitter enables multi-level cascading within the strict PCIe Gen5 jitter budget. Renesas’ high-performance oscillators and clock generators provide an ideal clock source for the enhanced PCIe clock buffer family. 

For more information about these PCIe Gen5 clock buffers, visit the PCIe timing page.

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