特性
- 12-bit pipelined ADC core
- Clock input divider by 2 for less jitter contribution
- CMOS or LVDS DDR digital outputs
- Duty cycle stabilizer
- Fast OuT of Range (OTR) detection
- Flexible input voltage range: 1 V p-p to 2 V p-p
- HVQFN40 package
- Input bandwidth, 600 MHz
- Integrated input buffer
- Offset binary, 2's complement, gray code
- Pin compatible with the ADC1415S series, ADC1115S series and the ADC1015S
- series
- Power-down and Sleep modes
- Sample rate up to 80 Msps
- Serial Peripheral Interface (SPI)
- SNR, 70.5 dBFS
- SFDR, 90 dBc
ADC1215S080HN - Block Diagram
描述
The ADC1215S is a single-channel 12-bit Analog-to-Digital Converter (ADC) optimized for high dynamic performances and low power consumption at sample rates up to 80 Msps. Pipelined architecture and output error correction ensure the ADC1215S is accurate enough to guarantee zero missing codes over the entire operating range. Supplied from a single 3 V source, it can handle output logic levels from 1.8 V to 3.3 V in CMOS mode. It supports the LVDS DDR output standard. An integrated SPI allows the user to easily configure the ADC. With excellent dynamic performance from the baseband to input frequencies of 170 MHz or more. The integrated input buffer ensures that the input impedance remains constant and low and the performance consistent over a wide frequency range.
