封装信息
| CAD 模型: | View CAD Model |
| Pkg. Type: | SBDIP |
| Pkg. Code: | DAV |
| Lead Count (#): | 16 |
| Pkg. Dimensions (mm): | 20.32 x 7.49 x 2.41 |
| Pitch (mm): | 2.54 |
环境和出口类别
| Moisture Sensitivity Level (MSL) | Not Applicable |
| Pb (Lead) Free | Exempt |
| ECCN (US) | |
| HTS (US) |
产品属性
| Pkg. Type | SBDIP |
| Lead Count (#) | 16 |
| Carrier Type | Tube |
| Moisture Sensitivity Level (MSL) | Not Applicable |
| Pitch (mm) | 2.5 |
| Pkg. Dimensions (mm) | 20.3 x 7.5 x 2.41 |
| DLA SMD | 5962R9662302VEC |
| Pb (Lead) Free | Exempt |
| Pb Free Category | Gold Plate over compliant Undercoat-e4 |
| MOQ | 25 |
| Temp. Range (°C) | -55 to +125°C |
| DSEE (MeV·cm2/mg) | 75 |
| Length (mm) | 20.3 |
| Qualification Level | QML Class V (space) |
| Rating | Space |
| TID HDR (krad(Si)) | 100 |
| TID LDR (krad(Si)) | ELDRS free |
| Thickness (mm) | 2.41 |
| Width (mm) | 7.5 |
有关 CD4021BMS 的资源
描述
CD4014BMS - synchronous parallel or serial input/serial output CD4021BMS - asynchronous parallel input or synchronous serial input/serial output CD4014BMS and CD4021BMS series types are 8-stage parallel or serial input/serial output registers having common CLOCK and PARALLEL/SERIAL CONTROL inputs, a single SERIAL data input, and individual parallel JAM inputs to each register stage. Each register stage is a D-type, master-slave flip-flop. In addition to an output from stage 8, Q outputs are also available from stages 6 and 7. Parallel as well as serial entry is made into the register synchronously with the positive clock line transition in the CD4014BMS. In the CD4021BMS serial entry is synchronous with the clock but parallel entry is asynchronous. In both types, entry is controlled by the PARALLEL/SERIAL CONTROL input. When the PARALLEL/SERIAL CONTROL input is low, data is serially shifted into the 8-stage register synchronously with the positive transition of the clock line. When the PARALLEL/ SERIAL CONTROL input is high, data is jammed into the 8-stage register via the parallel input lines and synchronous with the positive transition of the clock line. In the CD4021BMS, the CLOCK input of the internal stage is forced when an asynchronous parallel entry is made. Register expansion using multiple packages is permitted. The CD4014BMS and CD4021BMS are supplied in these 16-lead outline packages: Braze Seal DIP H4T Frit Seal DIP H1F Ceramic Flatpack H6W