封装信息
| CAD 模型: | View CAD Model |
| Pkg. Type: | PDIP |
| Pkg. Code: | EFJ |
| Lead Count (#): | 16 |
| Pkg. Dimensions (mm): | 19.05 x 6.60 x 3.94 |
| Pitch (mm): | 2.54 |
环境和出口类别
| Moisture Sensitivity Level (MSL) | Not Applicable |
| ECCN (US) | EAR99 |
| HTS (US) | 8542.39.0090 |
| Pb (Lead) Free | Yes |
产品属性
| Carrier Type | Tube |
| Moisture Sensitivity Level (MSL) | Not Applicable |
| Frequency Range (MHz) | 0.032 - 4 |
| IS (mA) | 0.08 |
| Lead Count (#) | 16 |
| Length (mm) | 19 |
| MOQ | 500 |
| Oscillator Type | CRYSTAL or EXT CLK |
| Pb (Lead) Free | Yes |
| Pb Free Category | Pb-Free 100% Matte Tin Plate w/Anneal-e3 |
| Pitch (mm) | 2.5 |
| Pkg. Dimensions (mm) | 19.0 x 6.6 x 3.94 |
| Pkg. Type | PDIP |
| Price (USD) | $25.11928 |
| Supply Voltage Vcc Range | 3-6 |
| Temp. Range (°C) | -40 to +85°C |
| Thickness (mm) | 3.94 |
| Width (mm) | 6.6 |
有关 CDP68HC68T1 的资源
描述
The CDP68HC68T1 Real-Time Clock provides a time/calendar function, a 32 byte static RAM, and a 3 wire Serial Peripheral Interface (SPI Bus). The primary function of the clock is to divide down a frequency input that can be supplied by the on-board oscillator in conjunction with an external crystal or by an external clock source. The internal oscillator can operate with a 32kHz, 1MHz, 2MHz, or 4MHz crystal. An external clock source with a 32kHz, 1MHz, 2MHz, 4MHz, 50Hz or 60Hz frequency can be used to drive the CDP68HC68T1. The time registers hold seconds, minutes, and hours, while the calendar registers hold day-of-week, date, month, and year information. The data is stored in BCD format. In addition, 12 or 24 hour operation can be selected. In 12 hour mode, an AM/PM indicator is provided. The T1 has a programmable output which can provide one of seven outputs for use elsewhere in the system. Computer handshaking is controlled with a wired-OR interrupt output. The interrupt can be programmed to provide a signal as the result of:
- An alarm programmed to occur at a predetermined combination of seconds, minutes, and hours.
- One of 15 periodic interrupts ranging from sub-second to once per day frequency.
- A power fail detect. The PSE output and the VSYS input are used for external power control. The CPUR output is available to reset the processor under power-down conditions. CPUR is enabled under software control and can also be activated via the CDP68HC68T1's watchdog. If enabled, the watchdog requires a periodic toggle of the CE pin without a serial transfer.