特性
- PLL clock driver for DDR (Double Data Rate) synchronous DRAM applications
- Spread spectrum clock compatible
- Operating frequency: 60MHz to 220MHz
- Low jitter (cycle-to-cycle): ±50ps
- Distributes one differential clock input to four differential clock outputs
- Enters low power mode and 3-state outputs when input CLK signal is less than 20MHz or PWRDWN is low
- Operates from a 2.5V supply
- Consumes <200μA quiescent current
- External feedback pins (FBIN, FBIN) are used to synchronize outputs to input clocks
描述
2.5V 1 to 4 differential clock distributor. Optimized for clock distribution in DDR SDRAM applications. Operating frequency: 60MHZ to 220MHz
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