EL4585CSZ-T13

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The EL4585 is a PLL (Phase Lock Loop) sub-system, designed for video applications and also suitable for general purpose use up to 36MHz. In video applications, this device generates a TTL/CMOS-compatible pixel clock (CLK OUT) which is a multiple of the TV horizontal scan rate and phase locked to it. The reference signal is a horizontal sync signal, TTL/CMOS format, which can be easily derived from an analog composite video signal with the EL4583 sync separator. An input signal to coast is provided for applications where periodic disturbances are present in the reference video timing such as VTR head switching. The lock detector output indicates correct lock. The divider ratio is four ratios for NTSC and four similar ratios for the PAL video timing standards by external selection of three control pins. These four ratios have been selected for common video applications including 8F_SC, 6F_SC, 27MHz (CCIR 601 format) and square picture elements used in some workstation graphics. To generate 4F_SC, 3F_SC, 13. 5MHz (CCIR 601 format) etc. , use the EL4584, which does not have the additional divide-by-two stage of the EL4585. For applications where these frequencies are inappropriate or for general purpose PLL applications the internal divider can be bypassed and an external divider chain used.