特性
- IMVP-IV™ Compliant CORE Regulator
- Single-Phase Power Conversion
- "Loss-less" Current Sensing for Improved Efficiency and Reduced Board Area
- Optional Discrete Precision Current Sense Resistor
- Internal Gate Drive and Boot-Strap Diode
- Precision CORE Voltage Regulation
- 0.8% System Accuracy Over-temperature
- 6-Bit Microprocessor Voltage Identification Input
- Programmable "Droop" and CORE Voltage Slew Rate to Comply with IMVP-IV™ Specification
- Discontinuous Mode Of Operation for Increased Light Load Efficiency in Deep and Deeper Sleep Mode
- Direct Interface with System Logic (STP_CPU and DPRSLPVR) for Deep and Deeper Sleep Modes of Operation
- Easily Programmable Voltage Setpoints for Initial "Boot", Deep Sleep and Deeper Sleep Modes
- Excellent Dynamic Response
- Combined Voltage Feed-Forward and Average Current Mode Control
- Overvoltage, Undervoltage and Overcurrent Protection
- Power-good Output with Internal Blanking During VID and Mode Changes
- User Programmable Switching Frequency of 250kHz to 500kHz
- Pb-Free Plus Anneal Available (RoHS Compliant)
描述
The ISL6218 Single-Phase Buck PWM control IC, with integrated half bridge gate driver, provides a precision voltage regulation system for advanced Pentium-M microprocessors in notebook computers. This control IC also features both input voltage feed-forward and average current mode control for excellent dynamic response, Loss-less current sensing using MOSFET rDS(ON), and user selectable switching frequencies from 250kHz to 500kHz per phase. The ISL6218 includes a 6-bit digital-to-analog converter (DAC) that dynamically adjusts the CORE PWM output voltage from 0. 700V to 1. 708V in 16mV steps, and conforms to the Intel IMVP-IV™ mobile VID specification. The ISL6218 also has logic inputs to select Active, Deep Sleep and Deeper Sleep modes of operation. A precision reference, remote sensing and proprietary architecture with integrated processor-mode compensated Droop provides excellent static and dynamic CORE voltage regulation. Another feature of the ISL6218 IC controller is the internal PGOOD delay circuit that holds the PGOOD pin low for 3ms to 12ms after the VCCP and VCC_MCH regulators are within regulation. This PGOOD signal is masked during VID changes. Output overvoltage and undervoltage are monitored and result in the converter latching off and PGOOD signal being held low. The overvoltage and undervoltage thresholds are 112% and 84% of the VID, Deep or Deeper Sleep setpoint. Overcurrent protection features a 32 cycle overcurrent shutdown. PGOOD, Overvoltage, Undervoltage and Overcurrent provide monitoring and protection for the microprocessor and power system. The ISL6218 IC is available in a 38 Ld TSSOP and 40 Ld QFN package.
| Part Number | Status | Samples | Stock | RoHS | Package | Lead Count (#) | Carrier Type | Moisture Sensitivity Level (MSL) | Pkg. Dimensions (mm) | Pb (Lead) Free | Pb Free Category | Temp. Range (°C) |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ISL6218CRZ | Obsolete | N/A | In Stock | RoHS:EN | QFN | 40# | Tube | 3 | 6.0 x 6.0 x 0.90 | Yes | Pb-Free 100% Matte Tin Plate w/Anneal-e3 | 0 to +70°C |
| ISL6218CRZ-T | Obsolete | N/A | Out of Stock | RoHS:EN | QFN | 40# | Reel | 3 | 6.0 x 6.0 x 0.90 | Yes | Pb-Free 100% Matte Tin Plate w/Anneal-e3 | 0 to +70°C |
| ISL6218CVZ | Obsolete | N/A | Out of Stock | RoHS:EN | TSSOP | 38# | Tube | 3 | 9.7 x 4.4 x 0.92 | Yes | Pb-Free 100% Matte Tin Plate w/Anneal-e3 | 0 to +70°C |
| ISL6218CVZ-T | Obsolete | N/A | Out of Stock | RoHS:EN | TSSOP | 38# | Reel | 3 | 9.7 x 4.4 x 0.92 | Yes | Pb-Free 100% Matte Tin Plate w/Anneal-e3 | 0 to +70°C |
| ISL6218CVZA | Obsolete | N/A | Out of Stock | RoHS:EN | TSSOP | 38# | Tube | 3 | 9.7 x 4.4 x 0.92 | Yes | Pb-Free 100% Matte Tin Plate w/Anneal-e3 | 0 to +70°C |
| ISL6218CVZA-T | Obsolete | N/A | Out of Stock | RoHS:EN | TSSOP | 38# | Reel | 3 | 9.7 x 4.4 x 0.92 | Yes | Pb-Free 100% Matte Tin Plate w/Anneal-e3 | 0 to +70°C |
- 产品变更通告英语PDF 326 KB 2021年5月21日
- EOL 通告英语PDF 216 KB PLC14003A 2014年3月12日
- EOL 通告英语PDF 179 KB PLC14003 2014年2月11日
- 产品变更通告英语PDF 151 KB PCN13064 2013年11月21日
- 产品变更通告英语PDF 222 KB PCN13025B 2013年10月25日
- 产品变更通告英语PDF 121 KB PCN11113A 2012年8月13日
- 产品变更通告英语PDF 120 KB PCN11113 2011年10月31日
- 产品变更通告英语PDF 248 KB PCN10055 2010年6月30日
- 应用说明英语PDF 397 KB an1684 2004年1月19日AI 生成的摘要: The document outlines important legal disclaimers and usage guidelines for semiconductor products. It emphasizes user responsibility for product design and safety, disclaims liability for damages, and clarifies no intellectual property licenses are granted. Products are categorized by quality grades with specific application recommendations. Users must comply with laws, avoid unauthorized modifications, and ensure safe use within specified conditions. Contact details for Renesas Electronics sales offices worldwide are provided.
- 应用说明英语PDF 509 KB an1681 2004年1月19日AI 生成的摘要: The document explains grounding techniques for PCB layouts using a dual op amp example on a single-layer copper board. It compares three grounding schemes: a center spine ground trace, an outer ground plane, and a split/star ground plane, highlighting the benefits of single-point grounding to minimize noise and antenna effects. It emphasizes following current paths, minimizing loop lengths, and ensuring close forward and return paths to reduce interference. The document also includes disclaimers on product use, quality grades, safety, and legal compliance.
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- 应用说明英语PDF 397 KB an1684 2004年1月19日AI 生成的摘要: The document outlines important legal disclaimers and usage guidelines for semiconductor products. It emphasizes user responsibility for product design and safety, disclaims liability for damages, and clarifies no intellectual property licenses are granted. Products are categorized by quality grades with specific application recommendations. Users must comply with laws, avoid unauthorized modifications, and ensure safe use within specified conditions. Contact details for Renesas Electronics sales offices worldwide are provided.
- 应用说明英语PDF 509 KB an1681 2004年1月19日AI 生成的摘要: The document explains grounding techniques for PCB layouts using a dual op amp example on a single-layer copper board. It compares three grounding schemes: a center spine ground trace, an outer ground plane, and a split/star ground plane, highlighting the benefits of single-point grounding to minimize noise and antenna effects. It emphasizes following current paths, minimizing loop lengths, and ensuring close forward and return paths to reduce interference. The document also includes disclaimers on product use, quality grades, safety, and legal compliance.
应用说明和白皮书 (2)
- 产品变更通告英语PDF 326 KB 2021年5月21日
- EOL 通告英语PDF 216 KB PLC14003A 2014年3月12日
- EOL 通告英语PDF 179 KB PLC14003 2014年2月11日
- 产品变更通告英语PDF 151 KB PCN13064 2013年11月21日查看更多 (11)
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