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概览

描述

The ISL62771 is fully compliant with AMD Fusion SVI 2. 0 and provides a complete solution for microprocessor and graphics processor core power. The ISL62771 controller supports two Voltage Regulators (VRs) with three integrated gate drivers. The Core VR supports 2-, or 1-phase configurations while the Northbridge VR supports 1-phase operation. The two VRs share a serial control bus to communicate with the AMD CPU and achieve lower cost and smaller board area compared with two-chip solutions. The PWM modulator is based on Intersil’s Robust Ripple Regulator R3™ Technology. Compared to traditional modulators, the R3 modulator can automatically change switching frequency for faster transient settling time during load transients and improved light-load efficiency. The ISL62771 has several other key features. Both outputs support DCR current sensing with single NTC thermistor for DCR temperature compensation or accurate resistor current sensing. Both outputs utilize remote voltage sense, adjustable switching frequency, OC protection and power-good.

特性

  • Supports AMD SVI 2.0 serial data bus interface
  • Serial VID clock frequency range 100kHz to 25MHz
  • Dual output controller with integrated drivers
  • Precision voltage regulation
  • 0.5% system accuracy over-temperature
  • 0.5V to 1.55V in 6.25mV steps
  • Enhanced load line accuracy
  • Supports multiple current sensing methods
  • Lossless inductor DCR current sensing
  • Precision resistor current sensing
  • Programmable 1- or 2-phase for the core output
  • Adaptive body diode conduction time reduction
  • Superior noise immunity and transient response
  • Output current and voltage telemetry
  • Differential remote voltage sensing
  • High efficiency across entire load range
  • Programmable VID offset and droop on both outputs
  • Programmable switching frequency for both outputs
  • Excellent dynamic current balance between phases
  • Protection: OCP/WOC, OVP, PGOOD and thermal monitor
  • Small footprint 40 Ld 5x5 TQFN package
  • Pb-free (RoHS compliant)

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应用

设计和开发

模型

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