封装信息
| CAD 模型: | View CAD Model |
| Pkg. Type: | VFQFPN |
| Pkg. Code: | NQQ100 |
| Lead Count (#): | 100 |
| Pkg. Dimensions (mm): | 8.0 x 8.0 x 0.55 |
| Pitch (mm): | 0.5 |
环境和出口类别
| Moisture Sensitivity Level (MSL) | 3 |
| Pb (Lead) Free | Yes |
| ECCN (US) | EAR99 |
| HTS (US) | 8542.39.0090 |
产品属性
| Lead Count (#) | 100 |
| Carrier Type | Tray |
| Moisture Sensitivity Level (MSL) | 3 |
| Qty. per Reel (#) | 0 |
| Qty. per Carrier (#) | 260 |
| Pb (Lead) Free | Yes |
| Pb Free Category | e3 Sn |
| Temp. Range (°C) | -40 to 105°C |
| Country of Assembly | TAIWAN |
| Country of Wafer Fabrication | TAIWAN |
| Additive Phase Jitter Typ RMS (fs) | 30 |
| Adjustable Phase | No |
| Advanced Features | Flexible Power Sequencing, Loss of Signal Indicator, Power Down Tolerant, Automatic Clock Parking, SMBus Write Protection |
| App Jitter Compliance | PCIe Gen1, PCIe Gen2, PCIe Gen3, PCIe Gen4, PCIe Gen5, PCIe Gen6, PCIe Gen7 |
| Architecture | Common, SRIS, SRNS |
| Channels (#) | 2 |
| Core Voltage (V) | 3.3 |
| Diff. Inputs | 1 |
| Diff. Output Signaling | LP-HCSL |
| Diff. Outputs | 24 |
| Family Name | RC19 |
| Function | Fanout Buffer |
| Input Freq (MHz) | 1 - 400 |
| Input Type | LVDS, HCSL |
| Inputs (#) | 1 |
| Lead Compliant | No |
| Length (mm) | 8 |
| Longevity | 2040 4月 |
| MOQ | 260 |
| Noise Floor (dBc/Hz) | -154 |
| Output Banks (#) | 1 |
| Output Enable (OE) Pins | -154 |
| Output Freq Range (MHz) | 1 - 400 |
| Output Impedance | 85 |
| Output Skew (ps) | 32 |
| Output Type | LP-HCSL |
| Output Voltage (V) | 0.8 |
| Outputs (#) | 24 |
| Pitch (mm) | 0.5 |
| Pkg. Dimensions (mm) | 8.0 x 8.0 x 0.55 |
| Pkg. Type | VFQFPN |
| Power Consumption Typ (mW) | 808 |
| Price (USD) | $3.83306 |
| Prog. Interface | SMBus, Side-Band |
| Supply Voltage (V) | 3.3 - 3.3 |
| Tape & Reel | No |
| Thickness (mm) | 0.55 |
| Width (mm) | 8 |
| 已发布 | No |
有关 RC19024 的资源
描述
The RC19024 is a 24-output PCIe Gen7 buffer that is backward compatible with earlier PCIe generations. The RC19024 provides ultra-low additive jitter and reduced in-to-out delay performance for better design margin and incorporates several features for easier and more robust design.