特性
- PCIe Gen5 附加相位抖动：6fs RMS
- PCIe Gen6 附加相位抖动：4fs RMS
- PCIe Gen7 附加相位抖动：2.6fs RMS
- DB2000Q附加相位抖动：10fs RMS
- 12kHz 至 20MHz 附加相位抖动：156.25MHz 时为 33fs RMS
- 掉电耐受（PDT）输入
- 灵活的启动時序（FSS）
- 丢失 CLKIN 时的自动时钟驻留（ACP）
- 展頻耐受性
- CLKIN 相容 HCSL 或 LVDS 信号电平
- -40 °C 至 +105 °C，1.8V ± 5% 工作溫度和電壓
- 可透過引脚或 SMBus 选擇：
- 33Ω、85Ω 或 100Ω 差分输出阻抗
- Output slew rate 输出信號斜率
- 输出振幅（A001 后缀）
- 9 个 SMBus 地址和誤写保护
描述
RC19104 是一个1.8V的4输出 PCIe Gen7 缓冲器，向下兼容早期的 PCIe 产品。 RC19104 提供超低的附加抖动並減少輸入對輸出的延迟時間，以获得更好的设计裕量并结合了多种功能，可实现更簡單和稳健的设计。
产品参数
| 属性 | 值 |
|---|---|
| Diff. Outputs | 4 |
| Diff. Output Signaling | LP-HCSL |
| Output Freq Range (MHz) | 1 - 400 |
| Diff. Inputs | 1 |
| Power Consumption Typ (mW) | 92 |
| Supply Voltage (V) | 1.8 - 1.8 |
| Output Type | LP-HCSL |
| Battery Backup | No |
| Battery Seal | No |
| CPU Supervisory Function POR | No |
| Crystal Frequency Trimming | No |
| Frequency Out Pin | No |
| Inputs (#) | 1 |
| Input Freq (MHz) | 1 - 400 |
| Additive Phase Jitter Typ RMS (fs) | 33 |
| Function | Fanout Buffer |
| Input Type | LVDS, HCSL |
| Output Banks (#) | 1 |
| Core Voltage (V) | 1.8V, 1.8V |
| Output Voltage (V) | 0.8 |
| Product Category | Clock Buffers & Drivers, PCI Express Clocks |
封装选项
| Pkg. Type | Pkg. Dimensions (mm) | Lead Count (#) | Pitch (mm) |
|---|---|---|---|
| VFQFPN | 4.0 x 4.0 x 0.9 | 28 | 0.4 |
产品对比
| RC19104A | 9DBL0452 | 9ZXL0451E | RC19004 | |
| Core Voltage (V) | 1.8 | 3.3 | 3.3 | 3.3 |
| Output Impedance | 34, 85, 100 | 85 | 85 | 85, 100 |
| App Jitter Compliance | PCIe Gen1, PCIe Gen2, PCIe Gen3, PCIe Gen4, PCIe Gen5, PCIe Gen6, PCIe Gen7 | PCIe Gen1, PCIe Gen2, PCIe Gen3, PCIe Gen4, PCIe Gen5, PCIe Gen6 | 25G EDR, DB2000Q, IF-UPI, PCIe Gen1, PCIe Gen2, PCIe Gen3, PCIe Gen4, PCIe Gen5, QPI, UPI | PCIe Gen1, PCIe Gen2, PCIe Gen3, PCIe Gen4, PCIe Gen5, PCIe Gen6, PCIe Gen7 |
| VOUT Slew-rate Control | Yes | No | No | Yes |
| Additive Jitter | 4fs | 13fs | - | 4fs |
| VOUT Amplitude Control | Yes | No | No | No |
应用
- 云和高性能计算
- nVME 存储
- 网络
- 加速器
| 器件号 | 状态 | 样品 | 供应期限 | 库存 | 封装 | Lead Count (#) | Carrier Type | Moisture Sensitivity Level (MSL) | Qty. per Reel (#) | Qty. per Carrier (#) | Pb (Lead) Free | Pb Free Category | Temp. Range (°C) |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RC19104A001GNL#BB0 | Active | Available | 2040 Apr | 有库存 | VFQFPN | 28# | Tray | 1 | 0 | 490# | Yes | e3 Sn | -40 to 105°C |
| RC19104A001GNL#KB0 | Active | N/A | 2040 Apr | 缺货 | VFQFPN | 28# | Reel | 1 | 2500# | 0 | Yes | e3 Sn | -40 to 105°C |
| RC19104AGNL#BB0 | Active | Available | 2040 Apr | 有库存 | VFQFPN | 28# | Tray | 1 | 0 | 490# | Yes | e3 Sn | -40 to 105°C |
| RC19104AGNL#KB0 | Active | N/A | 2040 Apr | 缺货 | VFQFPN | 28# | Reel | 1 | 2500# | 0 | Yes | e3 Sn | -40 to 105°C |
- 应用说明英语PDF 2.66 MB R31AN0080EU0102 Rev.1.02 2026年6月02日AI 生成的摘要: Layout recommendations focus on PCIe Buffer/Mux devices across several families, emphasizing optimal PCB layer stack-up, trace sizing, and signal routing. Key points include using microstrip impedance calculations and tools like Polar Instruments for trace design, following common layout rules such as avoiding right-angle bends, and ensuring proper power supply, clocking, EMI-EMC, and thermal layouts. The document provides detailed guidance on signal integrity, current return paths, crosstalk reduction, and EPAD thermal management to enhance PCIe timing device performance.
- 应用说明英语PDF 431 KB 7WDXRDKU4E7E-5-59216 2023年12月06日
- 白皮书英语PDF 1.35 MB 7WDXRDKU4E7E-6-61930 2020年8月05日As PCIe data rates increase and jitter budgets tighten, accurately measuring reference clock jitter becomes more challenging. This paper examines how intrinsic jitter in test setups impacts measurement accuracy and compares results from Phase Noise Analyzers and digital sampling oscilloscopes. It also explores methods to isolate and correct for intrinsic jitter using noiseless PCIe Gen5 clock sources and real-world components such as fan-out buffers and clock generators.
- 应用说明英语PDF 495 KB 7WDXRDKU4E7E-5-57312 2014年5月12日
- 应用说明英语PDF 160 KB 7WDXRDKU4E7E-5-57287 2014年5月06日
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- 应用说明英语PDF 2.66 MB R31AN0080EU0102 Rev.1.02 2026年6月02日AI 生成的摘要: Layout recommendations focus on PCIe Buffer/Mux devices across several families, emphasizing optimal PCB layer stack-up, trace sizing, and signal routing. Key points include using microstrip impedance calculations and tools like Polar Instruments for trace design, following common layout rules such as avoiding right-angle bends, and ensuring proper power supply, clocking, EMI-EMC, and thermal layouts. The document provides detailed guidance on signal integrity, current return paths, crosstalk reduction, and EPAD thermal management to enhance PCIe timing device performance.
- 应用说明英语PDF 431 KB 7WDXRDKU4E7E-5-59216 2023年12月06日
- 白皮书英语PDF 1.35 MB 7WDXRDKU4E7E-6-61930 2020年8月05日As PCIe data rates increase and jitter budgets tighten, accurately measuring reference clock jitter becomes more challenging. This paper examines how intrinsic jitter in test setups impacts measurement accuracy and compares results from Phase Noise Analyzers and digital sampling oscilloscopes. It also explores methods to isolate and correct for intrinsic jitter using noiseless PCIe Gen5 clock sources and real-world components such as fan-out buffers and clock generators.查看更多 (10)
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The RC family consists of PCIe Gen7 clock buffer and multiplexer solutions, providing the industry's smallest and most compact footprint.
Introducing Renesas’ enhanced PCIe clock buffer family. These PCIe Gen5 clock buffers offer fanout and zero-delay operating modes, supporting both legacy systems and the most complex timing trees within a single device. Unlike many existing solutions, whose performance limitations force their use in fanout buffer mode, these clock buffers meet both PCIe Gen5 and prominent CPU-specific phase jitter requirements in all operating modes. The extremely low 50fs rms PCIe Gen5 additive phase jitter enables multi-level cascading within the strict PCIe Gen5 jitter budget. Renesas’ high-performance oscillators and clock generators provide an ideal clock source for the enhanced PCIe clock buffer family.
A detailed overview of IDT's full-featured PCI Express (PCIe) clock and timing solutions. The presentation addresses PCIe Gen 1, Gen 2, Gen 3, and Gen 4 architectures and how IDT's industry-leading solutions provide all the functions, features, and performance required by the application.
Presented by Ron Wade, System Architect at IDT. For more information visit the PCIe clocks page.
The 9ZXL1951D is designed to create clocks for PCI Express Generation 4. This video demonstrates how the reference clock for the 9ZXL1951D does not need to be PCI Express Gen4 compliant. When using the Low Bandwidth mode, the 9ZXL1951D will attenuate jitter so its output clocks still pass PCI Express Gen4, even when the input clock only passes PCI Express Gen3. This is most useful when the clock has spread spectrum modulation because it is very difficult to make a very low noise spreading clock.
A brief overview of how data rates have changed from PCI Express (PCIe) Generation 1, Gen 2, Gen 3, Gen 4 and Gen 5.
Presented by Ron Wade, system architect at IDT.
A brief overview of how clock and timing specifications have changed from PCI Express (PCIe) Generation 1, Gen 2, Gen 3, Gen 4 and Gen 5.
Presented by Ron Wade, system architect at IDT (acquired by Renesas).
A brief overview of the PCI Express common clock (CC) jitter model, and the transfer functions as they relate to the timing PLLs. This model applies to PCI Express (PCIe) Gen 2, Gen 3, Gen 4 and Gen 5. The equations would be slightly different for other PCIe architectures, such as SRIS, SRnS, or data clocked.
Presented by Ron Wade, system architect at IDT (acquired by Renesas). For more information about Renesas's PCIe timing solutions, visit the PCI Express (PCIe) Clocks page.
This video compares PCIe Gen3–7 common clock jitter filters with a typical 12kHz to 20MHz plot to highlight the differences in filtering approaches.
