封装信息
| CAD 模型: | View CAD Model |
| Pkg. Type: | CABGA |
| Pkg. Code: | AKG176 |
| Lead Count (#): | 176 |
| Pkg. Dimensions (mm): | 13.5 x 8.0 x 1.1 |
| Pitch (mm): | 0.65 |
环境和出口类别
| Moisture Sensitivity Level (MSL) | 3 |
| Pb (Lead) Free | Yes |
| ECCN (US) | |
| HTS (US) |
产品属性
| Pkg. Type | CABGA |
| Lead Count (#) | 176 |
| Carrier Type | Tray |
| Moisture Sensitivity Level (MSL) | 3 |
| Qty. per Reel (#) | 0 |
| Qty. per Carrier (#) | 170 |
| Pb (Lead) Free | Yes |
| Pb Free Category | e1 SnAgCu |
| Temp. Range (°C) | 0 to 70°C |
| Function | Register + PLL |
| Length (mm) | 13.5 |
| MOQ | 340 |
| Package Area (mm²) | 108 |
| Pitch (mm) | 0.65 |
| Pkg. Dimensions (mm) | 13.5 x 8.0 x 1.1 |
| Requires Terms and Conditions | Does not require acceptance of Terms and Conditions |
| SDRAM Type | DDR3-800 to 1600 |
| Supply Voltage (V) | 1.35 - 1.35, 1.5 - 1.5 |
| Tape & Reel | No |
| Thickness (mm) | 1.1 |
| Width (mm) | 8 |
| 已发布 | No |
有关 SSTE32882HLB 的资源
描述
This 28-bit 1:2, or 26-bit 1:2 and 4-bit 1:1, registering clock driver with parity is designed for 1.35V and 1.5V VDD operation with parity is designed for 1.35V and 1.5V VDD operation.