时钟和时序

概览

The 9FGL0841/51 devices are 8-output 3.3V PCIe Gen1–5 clock generators. Each output has a dedicated OE# pin supporting PCIe CLKREQ# functionality. Two different spread spectrum levels, in addition to spread off, are supported. The 9FGL0841/51 supports PCIe Gen1–5 Common Clocked architectures (CC), PCIe Separate Reference no-Spread (SRNS) and Separate Reference Independent Spread (SRIS) clocking architectures.
 
For information regarding evaluation boards and material, please contact your local sales representative.
 
9FGL02-04-06-08 - Block Diagram
9FGL0841_51 - Pinout
9FGL02-04-06-08 - Block Diagram
9FGL0841_51 - Pinout
  • PCIe Gen1–5 CC-compliant
  • Supports PCIe SRIS and SRNS clocking
  • Integrated terminations for 100Ω and 85Ω systems save 4 resistors per output
  • Pin-selectable SRnS 0%, CC 0% and CC/SRIS -0.5% spread
  • SMBus-selectable CC/SRIS -0.25% spread
  • One 3.3V LVCMOS REF output with Wake-On-LAN (WOL) support
  • Easy AC-coupling to other logic families, see application note AN-891.
  • Space saving 6 × 6 mm 48-VFQFPN
Genoa 服务器解决方案

文档

文档标题 类型 日期
9FGL02x1-04x1-06x1-08x1D Datasheet
PDF545 KB
数据手册
AN-827 Application Relevance of Clock Jitter
PDF1.99 MB
应用文档
AN-975 Cascading PLLs
PDF255 KB
应用文档
AN-891 Driving LVPECL, LVDS, CML, and SSTL Logic with IDT Universal Low-Power HCSL Outputs
PDF480 KB
应用文档
AN-879 Low-Power HCSL vs Traditional HCSL
PDF235 KB
应用文档
AN-843 PCI Express Reference Clock Requirements
PDF1.90 MB
应用文档
AN-842 Thermal Considerations in Package Design and Selection
PDF495 KB
应用文档
AN-840 Jitter Specifications for Timing Signals
PDF442 KB
应用文档
AN-839 RMS Phase Jitter
PDF233 KB
应用文档
AN-835 Differential Input with VCMR being VIH Referenced
PDF160 KB
应用文档
AN-836 Differential Input to Accept Single-ended Levels
PDF120 KB
应用文档
AN-815 Understanding Jitter Units
PDF565 KB
应用文档
AN-802 Crystal-Measuring Oscillator Negative Resistance
PDF136 KB
应用文档
AN-805 Recommended Ferrite Beads
PDF121 KB
应用文档
9FGL02x1-04x1-06x1-08x1 Family Datasheet
PDF483 KB
数据手册
Timing Products for NXP (Freescale) i.MX (Chinese)
PDF512 KBEnglish
指南
9FGx08 PCIe Clock Generator Evaluation Boards User Guide
PDF838 KB
手册 - 硬件
PCI Express Timing Solutions Overview
PDF2.40 MB
概览
PA# : 220010 Register value update on 9DBL0xxxC, 9FGL0xxxD and 9SQL495xD product family
PDF171 KB
Product Advisory
PCN# : 220015 (R1) Add Alternate Assembly Location on VFQFPN Packages
PDF734 KB
产品变更通告
PCN# : 220011 (R1) New Revision for 9FGL/9DBL Family
PDF120 KB
产品变更通告
PCN# : 220015 Add Alternate Assembly Location on VFQFPN Packages
PDF728 KB
产品变更通告
PCN# : TP1910-02 Metal Change to Enhance Spread Performance
PDF127 KB
产品变更通告
PCN# : A1904-01 Add Greatek, Taiwan as an Alternate Assembly Facility
PDF983 KB
产品变更通告
PCN# : A1611-02 Add JCET China as Alternate Assembly and Change of Material Set at Alternate Assembly Location
PDF583 KB
产品变更通告
PCN# : MM1610-01 Improve performance to meet the new PCIe
PDF23 KB
产品变更通告
9FGL08xx EVB Reference Schematic
PDF34 KB
原理图

设计和开发

软件下载

文档标题 类型 日期
Software for PCIe Evaluation Kits
ZIP440 KB
软件和工具 - 评估软件

开发板与套件

EVK9FGL0841

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立即订购

Evaluation Board for the 100ohm 9FGL0841 PCIe Clock Generator

This is the evaluation board for the 9FGL0841 clock generator. 

特色文件:
9FGx08 PCIe Clock Generator Evaluation Boards User Guide

EVK9FGL0851

评估
立即订购

Evaluation Board for the 85ohm 9FGL0851 PCIe Clock Generator

This is the evaluation board for the 9FGL0851 clock generator. 

特色文件:
9FGx08 PCIe Clock Generator Evaluation Boards User Guide

ECAD 模块

Schematic symbols, PCB footprints, and 3D CAD models from SamacSys can be found by clicking on products in the Product Options table. If a symbol or model isn't available, it can be requested directly from the website.

扩展 ECAD 模块

模块

Title Type Date
9FGL0841 IBIS Model
ZIP89 KB
模型 - IBIS
9FGL08P1 IBIS Model
ZIP203 KB
模型 - IBIS

产品选择

    Processing table
    器件号
    Pkg. Type
    Lead Count (#)
    Temp. Grade
    Output Impedance
    Carrier Type
    购买 / 样片
    9FGL0841DKILF
    play_circleActive
    memory
    view_in_ar
    可提供样品
    		 VFQFPN 48 I 100 Tray 获取样片,
    9FGL0841DKILFT
    play_circleActive
    memory
    view_in_ar
    可提供样品
    		 VFQFPN 48 I 100 Reel 获取样片,
    9FGL0851DKILF
    play_circleActive
    memory
    view_in_ar
    可提供样品
    		 VFQFPN 48 I 85 Tray 获取样片,
    9FGL0851DKILFT
    play_circleActive
    memory
    view_in_ar
    		VFQFPN 48 I 85 Reel
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    支持

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    视频和培训

    PCIe Reference Clock Jitter Budgets

    IDT’s chief PCIe system architect explains the fundamental difference in reference clock jitter budgets between the first three generations of the specification and those of Gen4 and Gen5 which raise new challenges for designers.

    Video List

    新闻和博客

    IDT Adds 3.3 V PCIe Clock Generators to World’s Lowest Power PCI Express Timing Family 新闻