特性
- PCIe Gen 1–6 CC-compliant
- Supports PCIe SRIS and SRNS clocking
- Integrated terminations for 100Ω and 85Ω systems save 4 resistors per output
- Pin-selectable SRNS 0%, CC 0%, and CC/SRIS -0.5% spread
- SMBus-selectable CC/SRIS -0.25% spread
- One 3.3V LVCMOS REF output with Wake-On-LAN (WOL) support
- Easy AC coupling to other logic families, see application note AN-891.
- Space-saving 6mm × 6mm 48-VFQFPN
描述
The 9FGL0841/51 devices are 8-output 3.3V PCIe Gen 1–6 clock generators. Each output has a dedicated OE# pin supporting PCIe CLKREQ# functionality. Two different spread spectrum levels, in addition to spread off, are supported. The 9FGL0841/51 supports PCIe Gen 1–6 Common Clocked architectures (CC), PCIe Separate Reference no Spread (SRNS), and Separate Reference Independent Spread (SRIS) clocking architectures.
For information regarding evaluation boards and material, please contact your local sales representative.
产品参数
| 属性 | 值 |
|---|---|
| Diff. Outputs | 8 |
| App Jitter Compliance | PCIe Gen1, PCIe Gen2, PCIe Gen3, PCIe Gen4, PCIe Gen5, PCIe Gen6 |
| Outputs (#) | 9 |
| Output Type | LP-HCSL, LVCMOS |
| Output Freq Range (MHz) | 25 - 25, 100 - 100 |
| Input Freq (MHz) | 25 - 25 |
| Inputs (#) | 1 |
| Input Type | Crystal, LVCMOS |
| Core Voltage (V) | 3.3 |
| Output Voltage (V) | 0.8V, 3.3V |
| Product Category | PCI Express Clocks |
封装选项
| Pkg. Type | Pkg. Dimensions (mm) | Lead Count (#) | Pitch (mm) |
|---|---|---|---|
| VFQFPN | 6.0 x 6.0 x 0.9 | 48 | 0.4 |
应用方框图
 | AMD 第四代 EPYC（Genoa）电源和定时系统 适用于 AMD Genoa 的完整电源和时序系统，支持 SVI3、DDR5 和 PCIe Gen 5/6。 |