瑞萨电子 (Renesas Electronics Corporation)
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9FGV1006

有效
Product Longevity: 2040

Programmable PhiClock Generator

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概览

The 9FGV1006 is a member of Renesas' PhiClock™ programmable clock generator family. The 9FGV1006 provides two copies of a single integer, fractional or spread-spectrum output frequency and one copy of the crystal reference input. Two select pins allow for hardware selection of the desired configuration, or two I²C bits all easy software selection of the desired configuration. The user may configure any one of the four OTP configurations as the default when operating in I²C mode. Four unique I²C addresses are available, allowing easy I²C access to multiple components.

9FGV1002C_9FGV1006C - Block Diagram
9FGV1006C - Pinout
9FGV1002C_9FGV1006C - Block Diagram
9FGV1006C - Pinout
  • PCIe Gen 1–7 compliant
  • PCIe Gen 7 Common Clock jitter < 41fs RMS
  • 276fs RMS typical phase jitter at 156.25MHz (12kHz to 20MHz)
  • 2 programmable output pairs plus 1 LVCMOS REF output
  • 1 integer, fractional or spread-spectrum output frequency per configuration
  • 1MHz to 325MHz output frequency (LVDS or LP-HCSL)
  • 1MHz to 200MHz output frequency (LVCMOS)
  • 1.8V to 3.3V core VDD
  • Individual 1.8V, 2.5V, or 3.3V VDDO for each programmable output pair
  • Supports HCSL, LVDS, and LVCMOS I/O standards
  • Supports AC-coupled LVPECL and CML logic – See AN-891
  • 3mm × 3mm 16-LGA packages with 50MHz integrated crystal option
  • Supported by Timing Commander™ software

文档

设计和开发

软件下载
类型 文档标题 日期
软件和工具 - 软件
I2C GUI Tool Software
ZIP 9.27 MB
软件和工具 - 其他
9FGV100x Fractional Timing Commander Personality File v1.4.2
7Z 6.19 MB
2 项目
9FGV1006 - Evaluation Board (perspective).png
评估
EVK9FGV1006 有效

Evaluation Kit for 9FGV1006 Programmable PhiClock™ Generator

This is the evaluation board for the 9FGV1006 programmable PhiClockTM generator. It provides a convenient way of configuring and programming the blank parts for the 9FGV1006 device. With the onboard USB interface, the Renesas Timing CommanderTM graphical user interface (GUI) can communicate with...

推荐文档：
9FGV1006 / 9FGV1008 PhiClock PCIe Evaluation Board User Guide
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9FGV1006 - Evaluation Board (perspective).png
评估
EVK9FGV1006Q5 有效

Evaluation Kit for 9FGV1006 Programmable PhiClock™ Generator with Internal 50MHz Crystal

This is the evaluation board for the 9FGV1006Q5 programmable PhiClockTM generator with an internal 50MHz crystal. It provides a convenient way of configuring and programming the blank parts for the 9FGV1006Q5 device. With the onboard USB interface, the Renesas Timing CommanderTM graphical user...

推荐文档：
9FGV1006 / 9FGV1008 PhiClock PCIe Evaluation Board User Guide
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ECAD 模块

点击产品选项表中的 CAD 模型链接，查找 SamacSys 中的原理图符号、PCB 焊盘布局和 3D CAD 模型。如果符号和模型不可用，可直接在 SamacSys 请求该符号或模型。

扩展 ECAD 模块
Diagram of ECAD Models

模型
类型 文档标题 日期
模型 - IBIS
9FGV100x IBIS Model
ZIP 106 KB
1 项目
此为出厂可配置设备。试用自定义部件配置工具。

产品选项

当前筛选条件

视频和培训

PCIe Reference Clock Jitter Budgets

Ron Wade, chief PCIe system architect explains the fundamental difference in reference clock jitter budgets between the first three generations of the specification and those of Gen4 and Gen5 which raise new challenges for designers.

Related Resources

 

Video List
PCIe Reference Clock Jitter Budgets
PCIe Data Rates vs Clock Jitter Specs
What Does PCIe Gen5 Say About SRIS?
IDT PhiClock™ PCIe Gen 4 Clock Generators, 9FGV100x Family
PCI Express (PCIe) Clock Overview by IDT
PCIe Clocking Architectures (Common and Separate)
PCIe Common Clock Architecture and its Impact on Clocking
PCIe Separate Reference without Spread Clock Architecture
PCIe Separate Reference Clock With Independent Spread (SRIS) Architecture Overview
Standard HCSL vs. Low-Power HCSL (LP-HCSL) Output Signaling
PCI Express (PCIe) Clock Generators by IDT
PCI Express (PCIe) Clock Applications Overview
PCI Express Gen 1 to Gen 4/Gen 5 Data Rate Evolution
PCI Express Gen 1 to Gen 4/Gen 5 Clock Specification Evolution
PCI Express Common Clock Jitter Model and Transfer Functions
Comparing PCI Express Gen3-7 Jitter Filters to a 12k-20M Jitter Filter

新闻和博客

博客
2022年4月14日
Solving Common Issues with Respect to PCIe Timing Design on the Modern Server System
博客
2019年6月15日
Faster Timing Design and Accurate Performance Testing with Jitter Measurement Utility
博客
2018年5月22日
Comparing and Contrasting PCIe and Ethernet Clock Jitter Specifications
新闻
2018年4月30日
IDT Extends Leadership in Datacenter and Networking Systems with Launch of Its Latest PCI Express Timing Devices