时钟和时序

概览

The 9FGV1006 is a member of Renesas' PhiClock™ programmable clock generator family. The 9FGV1006 provides 2 copies of a of a single integer, fractional or spread-spectrum output frequency and one copy of the crystal reference input. Two select pins allow for hardware selection of the desired configuration, or two I²C bits all easy software selection of the desired configuration. The user may configure any one of the four OTP configurations as the default when operating in I²C mode. Four unique I²C addresses are available, allowing easy I²C access to multiple components.

9FGV1002C_9FGV1006C - Block Diagram
9FGV1006C - Pinout
9FGV1002C_9FGV1006C - Block Diagram
9FGV1006C - Pinout
  • PCIe Gen1–6 compliant
  • PCIe Gen6 Common Clock jitter < 50fs RMS
  • 276fs RMS typical phase jitter at 156.25MHz (12kHz–20MHz)
  • 2 programmable output pairs plus 1 LVCMOS REF output
  • 1 integer, fractional or spread-spectrum output frequency per configuration
  • 1MHz–325MHz output frequency (LVDS or LP-HCSL)
  • 1MHz–200MHz output frequency (LVCMOS)
  • 1.8V to 3.3V core VDD
  • Individual 1.8V, 2.5V or 3.3V VDDO for each programmable output pair
  • Supports HCSL, LVDS and LVCMOS I/O standards
  • Supports AC-coupled LVPECL and CML logic – see AN-891
  • 3 × 3 mm 16-LGA packages with 50MHz integrated crystal option
  • Supported by Timing Commander™ software
PCIe 非易失性存储器 Express (NVMe) 固态硬盘解决方案
Xilinx UltraScale+ RFSoC Gen 1/2 ZU2x/3x 电源和时序
Xilinx Versal ACAP 电源和时序

文档

文档标题 类型 日期
9FGV1002C-9FGV1006C Datasheet
PDF442 KB
数据手册
AN-827 Application Relevance of Clock Jitter
PDF1.99 MB
应用文档
How to Make 1.2V LVCMOS from 1.8V LVCMOS Output
PDF256 KB
应用文档
Driving Differential, Single-Ended, and/or Frequency Generator Crystal Inputs
PDF134 KB
应用文档
9FGV100x: PhiClock OTP Procedure
PDF222 KB
应用文档
AN-1014 Microstrip vs Stripline: Crosstalk and RMS Phase Jitter
PDF486 KB
应用文档
AN-1001 Combining PhiClock and 9ZXL1951D for PCIe Gen4/5
PDF244 KB
应用文档
AN-975 Cascading PLLs
PDF255 KB
应用文档
AN-918 Programmable Clocks vs Crystal Oscillators
PDF307 KB
应用文档
AN-891 Driving LVPECL, LVDS, CML, and SSTL Logic with IDT Universal Low-Power HCSL Outputs
PDF480 KB
应用文档
AN-879 Low-Power HCSL vs Traditional HCSL
PDF235 KB
应用文档
AN-843 PCI Express Reference Clock Requirements
PDF1.90 MB
应用文档
AN-842 Thermal Considerations in Package Design and Selection
PDF495 KB
应用文档
AN-840 Jitter Specifications for Timing Signals
PDF442 KB
应用文档
AN-839 RMS Phase Jitter
PDF233 KB
应用文档
AN-835 Differential Input with VCMR being VIH Referenced
PDF160 KB
应用文档
AN-836 Differential Input to Accept Single-ended Levels
PDF120 KB
应用文档
AN-815 Understanding Jitter Units
PDF565 KB
应用文档
AN-802 Crystal-Measuring Oscillator Negative Resistance
PDF136 KB
应用文档
AN-805 Recommended Ferrite Beads
PDF121 KB
应用文档
9FGV1006C001 Datasheet Addendum
PDF144 KB
数据手册
9FGV1006C002 Datasheet Addendum
PDF144 KB
数据手册
9FGV1006C015 Datasheet Addendum
PDF144 KB
数据手册
9FGV1006CQ505 Datasheet Addendum
PDF144 KB
数据手册
9FGV1006CQ506 Datasheet Addendum
PDF144 KB
数据手册
9FGV1006CQ515 Datasheet Addendum
PDF144 KB
数据手册
9FGV1006 Register Descriptions and Programming Guide
PDF323 KB
手册 - 软件
9FGV1006 Timing Commander User Guide
PDF1.49 MB
手册 - 软件
9FGV100x Register Descriptions and Programming Guide
PDF401 KB
手册 - 软件
I2C GUI Tool User Guide
PDF507 KB
其他
PCI Express Timing Solutions Overview
PDF2.40 MB
概览
PCN# : PCN200009 (R1) PhiClock Family Revision Update
PDF129 KB
产品变更通告
PCN# : PCN200009 PhiClock Family Revision Update
PDF143 KB
产品变更通告
PCN# : MM1809-01 Die revision change,9FGV1006AnnnLTGI (8), 9FGV1006Q5nnLTGI (8)
PDF761 KB
产品变更通告
PCIe Reference Clock Jitter Measurements for Gen5 and Beyond
PDF1.35 MB
白皮书

设计和开发

软件下载

文档标题 类型 日期
9FGV100x Fractional Timing Commander Personality File v1.4.2
7Z6.19 MB
软件和工具 - 其他
I2C GUI Tool Software
ZIP9.27 MB
软件和工具 - 软件

开发板与套件

9FGV1006 - Evaluation Board (perspective)

EVK9FGV1006

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Evaluation Kit for 9FGV1006 Programmable PhiClock™ Generator

This is the evaluation board for the 9FGV1006 programmable PhiClockTM generator. It provides a convenient way of configuring and programming the blank parts for the...

特色文件:
9FGV1006 / 9FGV1008 PhiClock PCIe Evaluation Board User Guide

ECAD 模块

Schematic symbols, PCB footprints, and 3D CAD models from SamacSys can be found by clicking on products in the Product Options table. If a symbol or model isn't available, it can be requested directly from the website.

扩展 ECAD 模块

模块

Title Type Date
9FGV1006 IBIS Model
ZIP87 KB
模型 - IBIS

产品选择

此为出厂可配置设备。试用自定义部件配置工具。
    Processing table
    Part Number
    Output Type
    Output Impedance
    Supply Voltage (V)
    Xtal Freq (MHz)
    Carrier Type
    Buy / Sample
    9FGV1006C001LTGI
    play_circleActive
    memory
    view_in_ar
    shopping_cartSamples Available
    		 LP-HCSL 100 3.3 25 Tray
    9FGV1006C001LTGI8
    play_circleActive
    memory
    view_in_ar
    		LP-HCSL 100 3.3 25 Reel
    9FGV1006C002LTGI
    play_circleActive
    memory
    view_in_ar
    shopping_cartSamples Available
    		 LP-HCSL 100 1.8 25 Tray
    9FGV1006C002LTGI8
    play_circleActive
    memory
    view_in_ar
    		LP-HCSL 100 1.8 25 Reel
    9FGV1006C015LTGI
    play_circleActive
    memory
    view_in_ar
    shopping_cartSamples Available
    		 LP-HCSL 85 3.3 25 Tray
    9FGV1006C015LTGI8
    play_circleActive
    memory
    view_in_ar
    		LP-HCSL 85 3.3 25 Reel
    9FGV1006CQ505LTGI
    play_circleActive
    memory
    view_in_ar
    shopping_cartSamples Available
    		 LP-HCSL 100 3.3 50 Tray
    9FGV1006CQ505LTGI8
    play_circleActive
    memory
    view_in_ar
    		LP-HCSL 100 3.3 50 Reel
    9FGV1006CQ506LTGI
    play_circleActive
    memory
    view_in_ar
    shopping_cartSamples Available
    		 LP-HCSL 100 1.8 50 Tray
    9FGV1006CQ506LTGI8
    play_circleActive
    memory
    view_in_ar
    		LP-HCSL 100 1.8 50 Reel
    9FGV1006CQ515LTGI
    play_circleActive
    memory
    view_in_ar
    shopping_cartSamples Available
    		 LP-HCSL 85 3.3 50 Tray
    9FGV1006CQ515LTGI8
    play_circleActive
    memory
    view_in_ar
    		LP-HCSL 85 3.3 50 Reel
    Parametric Table tips

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    • Document icon next to product name in row: View the featured document for this product
    • Chip icon next to the right of the document icon in row: View the block diagram for this product
    • Cart icon to the right of the chip icon: Indicates that samples are available for this product

    视频和培训

    PCIe Reference Clock Jitter Budgets

    IDT’s chief PCIe system architect explains the fundamental difference in reference clock jitter budgets between the first three generations of the specification and those of Gen4 and Gen5 which raise new challenges for designers.

    Video List

    新闻和博客

    Solving Common Issues with Respect to PCIe Timing Design on the Modern Server System 博客 2022年4月14日
    Faster Timing Design and Accurate Performance Testing with Jitter Measurement Utility 博客 2019年6月14日
    Comparing and Contrasting PCIe and Ethernet Clock Jitter Specifications 博客 2018年5月22日
    IDT Extends Leadership in Datacenter and Networking Systems with Launch of Its Latest PCI Express Timing Devices 新闻
    IDT Announces World’s Lowest-power PCI Express Timing Family 新闻