时钟和时序

概览

The ICS8543-09 is a low skew, high performance1-to-4 Differential-to-LVDS Clock Fanout Buffer. Utilizing Low Voltage Differential Signaling (LVDS) the ICS8543-09 provides a low power, low noise, solution for distributing clock signals over controlled impedances of 100Ω. The ICS8543-09 has two selectable clock inputs. The CLK, nCLK pair can accept most standard differential input levels. The PCLK, nPCLK pair can accept LVPECL, CML, or SSTL input levels. The clock enable is internally synchronized to eliminate runt pulses on the outputs during asynchronous assertion/deassertion of the clock enable pin.
 
Guaranteed output and part-to-part skew characteristics make the ICS8543-09 ideal for those applications demanding well defined performance and repeatability.
8543-09 Block Diagram
8543-09 - Pin Assignment
8543-09 Block Diagram
8543-09 - Pin Assignment
  • Four differential LVDS output pairs
  • Selectable differential CLK, nCLK or LVPECL clock inputs
  • CLK, nCLK pair can accept the following differential
    input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL
  • PCLK, nPCLK supports the following input types:
    LVPECL, CML, SSTL
  • Maximum output frequency: 800MHz
  • Translates any single-ended input signal to LVDS levels with
    resistor bias on nCLK input
  • Additive phase jitter, RMS: 0.146ps (typical)
  • Output skew: 100ps (maximum)
  • Part-to-part skew: 700ps (maximum)
  • Propagation delay: 3.3ns (maximum)
  • Full 3.3V supply mode
  • 0°C to 70°C ambient operating temperature
  • Available in lead-free (RoHS 6) package
  • Industrial temperature information available upon request

文档

文档标题 类型 日期
8543-09 Data Sheet
PDF1.23 MB
数据手册
AN-805 Recommended Ferrite Beads
PDF91 KB
应用文档
AN-827 Application Relevance of Clock Jitter
PDF1.99 MB
应用文档
AN-828 Termination - LVPECL
PDF322 KB
应用文档
AN-844 Termination - AC Coupling Clock Receivers
PDF170 KB
应用文档
AN-846 Termination - LVDS
PDF133 KB
应用文档
AN-842 Thermal Considerations in Package Design and Selection
PDF495 KB
应用文档
AN-840 Jitter Specifications for Timing Signals
PDF442 KB
应用文档
AN-833 Differential Input Self Oscillation Prevention
PDF180 KB
应用文档
AN-834 Hot-Swap Recommendations
PDF153 KB
应用文档
AN-835 Differential Input with VCMR being VIH Referenced
PDF160 KB
应用文档
AN-836 Differential Input to Accept Single-ended Levels
PDF120 KB
应用文档
AN-815 Understanding Jitter Units
PDF565 KB
应用文档
PDN# : TP-20-05(R1) Revised PDN - Change Replacement for 85411AMLF(T) from 5PB1102CMGI(8) to 8SLVP1102ANLGI(8)
PDF743 KB
End Of Life Notice
PDN# : TP-20-05 End-of-Life (EOL) Process on Select Part Numbers
PDF715 KB
End Of Life Notice
PDN# : N-12-22R2 PRODUCT DISCONTINUANCE NOTICE
PDF363 KB
End Of Life Notice
PDN# : N-12-22R1 PRODUCT DISCONTINUANCE NOTICE
PDF209 KB
End Of Life Notice
Clock Distribution Overview
PDF217 KB
概览
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PDF611 KB
产品变更通告
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PDF611 KB
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PDF596 KB
产品变更通告
PCN# : A1511-01 Add SPEL India as Alternate Assembly Location
PDF544 KB
产品变更通告
PCN# : TB1504-01R1 Qty per Reel Standardization for Selective Packages
PDF95 KB
产品变更通告
PCN# : TB1504-01 Qty per Reel Standardization for Selective Packages
PDF50 KB
产品变更通告
PCN# : TB1303-02 Change of Tape & Reel Packing Method for Selective Products
PDF361 KB
产品变更通告

设计和开发

软件下载

文档标题 类型 日期
PDN# : TP-20-05(R1) Revised PDN - Change Replacement for 85411AMLF(T) from 5PB1102CMGI(8) to 8SLVP1102ANLGI(8)
PDF743 KB
End Of Life Notice
PDN# : TP-20-05 End-of-Life (EOL) Process on Select Part Numbers
PDF715 KB
End Of Life Notice
PDN# : N-12-22R2 PRODUCT DISCONTINUANCE NOTICE
PDF363 KB
End Of Life Notice
PDN# : N-12-22R1 PRODUCT DISCONTINUANCE NOTICE
PDF209 KB
End Of Life Notice

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产品选择

    Processing table
    器件号
    Pkg. Type
    Lead Count (#)
    Temp. Grade
    Pb (Lead) Free
    Carrier Type
    购买 / 样片
    8543AG-09LF
    block_flippedObsolete
    memory
    view_in_ar
    		TSSOP 20 C Yes Tube
    8543AG-09LFT
    block_flippedObsolete
    memory
    view_in_ar
    		TSSOP 20 C Yes Reel
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