概览
描述
The 8T49N240 FemtoClock™ NG Universal Frequency Translator (UFT) has one fractional-feedback PLL that can be used as a frequency translator with jitter attenuation or a frequency synthesizer. It is equipped with three integer and one fractional output dividers, allowing the generation of up to two different output frequencies, ranging from 8kHz to 1GHz. Output frequencies can be completely independent of the input frequencies, two of these frequencies can be completely independent of each other and the other two will be integer-related to one of the other two frequencies. The four outputs may select among LVPECL, LVDS, HCSL, or LVCMOS output levels.
The 8T49N240 is ideal for use in a wide range of equipment, including 10G/40G/100G SONET/SDH and Ethernet network line cards, wireless base station baseband units, broadcast video, carrier Ethernet switches, OTN, or in test and measurement applications. For example, the 8T49N240 can be used in GbE/10GbE/100GbE Synchronous Ethernet line card applications to preserve the G.8262 compliance from the Synchronous Equipment Timing Source (SETS) on the timing card. The 8T49N240 provides a 200fs (typical, 12kHz to 20MHz) RMS jitter performance that provides users with additional margin in their designs.
Renesas’ third-generation Universal Frequency Translator family also includes the 8T49N241 (2-in/1-PLL/4-out), 8T49N242 (2-in/1-PLL/4-out), the 8T49N285 (2-in/1-PLL/8-out), the 8T49N286 (4-in/2-PLL/8-out) and the 8T49N287 (2-in/2-PLL/8-out). These devices are complemented by the 82P33714 and 82P33731 Synchronous Equipment Timing Source for Synchronous Ethernet (SyncE) and 10G to 40G SyncE, respectively.
To see other devices in this product family, visit the Universal Frequency Translators page.
特性
- Compliant with the requirements outlined in Telcordia GR-253-CORE (SONET) and ITU-T G.813/G.8262 (SDH/SONET and SyncE) when paired with a Synchronous Equipment Timing Source (SETS ) device
- Generates up to 4 LVPECL/LVDS/HCSL or 16 LVCMOS output clocks ranging from 8kHz up to 1.0GHz (diff), 8kHz to 250MHz (LVCMOS), that meet jitter limits for 10G up to 25G Ethernet applications
- 0.2ps RMS (including spurs), 12kHz to 20MHz
- Accepts up to two LVPECL, LVDS, LVHSTL, HCSL, or LVCMOS input clocks ranging from 8kHz up to 875MHz
- Auto and manual input clock selection with hitless switching
- Clock input monitoring, including support for gapped clocks
- Phase-Slope Limiting and Fully Hitless Switching options to control output phase transients
- Operates from a 25MHz to 50MHz crystal
- Register programmable through I²C or via external I²C EEPROM
- 8T49N240-991 “Boot from EEPROM”
- 8T49N240-994 “powers up disabled”
- Supported by Renesas' Timing Commander™ software
产品对比
应用
设计和开发
软件与工具
软件与工具
| Software title
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Software type
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公司
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| Timing Commander Timing Commander™ 是一个基于 Windows™ 的创新软件平台，通过这个平台，系统设计工程师可以通过直观且灵活的图形用户界面 (GUI) 对精密的计时设备进行配置、编程和监控。
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Code Generator | 瑞萨电子 |
1 项目
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开发板与套件
评估
8T49N240-EVK
有效
Evaluation Kit for 8T49N240
The 8T49N240-EVK is designed to help the customer evaluate the 8T49N240 Universal Frequency Translator (UFT 3G). When the board is connected to a PC running Timing Commander software™ through USB, the device can be configured and programmed through a graphical interface or through register...
模型
ECAD 模块
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视频和培训
IDT 8T49N240 Programmable Clock Generator and Jitter Attenuator for 10Gbps, 40Gbps, and 100Gbps
An overview of the IDT® 8T49N240, highly programmable clock generator and jitter attenuator IC. The device features less than 200fs of phase noise, providing valuable system design margin for 10Gbps interfaces in wireline and wireless communication networks. The additional phase noise margin eases system design constraints, allowing engineers to minimize bit error rates (BER) while lowering overall system costs.
The 8T49N240 is the latest member of IDT's third-generation Universal Frequency Translator (UFT™) family. It features the ability to produce virtually any common output frequency from virtually any input frequency. The highly flexible, high-performance clock generator and jitter attenuator is ideal for 10Gbps or multi-lane 40Gpbs / 100Gbps timing applications where 300fs of phase noise is typically the maximum acceptable amount allowed at the physical ports. The 200fs phase noise specification of the 8T49N240 provides ample noise margin, enabling engineers to simplify their clock tree designs and utilize lower cost PCBs.
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