概览
描述
This is the evaluation kit for the Renesas 8A34043 ClockMatrix Multichannel Digital PLLs (DPLLs)/Digitally Controlled Oscillators (DCOs). The 8A34043 provides four independent timing channels that can be configured as DPLLs or as DCOs. The DPLL channels can be used for jitter attenuation and frequency translation. The DCOs can be programmed to synthesize the desired frequency and they can be steered by external software with resolution of 1.11E-16. The DPLLs can lock to virtually any frequency from 1kHz to 1GHz and the DPLLs and DCOs can generate virtually any frequency from 0.5Hz to 1GHz with typical jitter below 150fs RMS from 12kHz to 20MHz.
特性
- 2 differential clock inputs
- 12 differential outputs
- 1 serial port channel
- On-board EEPROM
- 7 GPIO controls
- Selectable voltage controls
应用
设计和开发
模型
ECAD 模块
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