Evaluation Kit for RC32614A ClockMatrix

This is the evaluation kit for the Renesas RC32614A ClockMatrix System Synchronizer for IEEE 1588. The RC32614A provides six independent timing channels that can be configured as Digital PLLs (DPLLs) or as Digitally Controlled Oscillators (DCOs). The DPLL channels meet synchronous Ethernet requirements and they can be used for jitter attenuation and frequency translation. The DCOs they can be programmed to synthesize the desired frequency and can be steered by external software with resolution of 1.11E-16. The DPLLs can lock to virtually any frequency from 0.5Hz to 1GHz and the DPLLs and DCOs can generate virtually any frequency from 0.5Hz to 1GHz with ultra-low phase noise <100fs RMS from 12kHz to 20MHz.