特性
- Packaged in 8 pin SOIC (Pb-free) or die
- Separate VDD supplies allow voltage translation
- Clock frequency of 0 - 250 MHz
- Duty cycle of 45/55
- Operating voltages of 2.375 to 5.5V
- Tri-state output for board level testing
- 24mA output drive capability
- Industrial temperature version available
- Advanced, low power, sub-micron CMOS process
508 - Block Diagram
描述
The 508 is the most cost effective way to generate a high quality, high frequency CMOS clock output from a PECL clock input. The 508 has separate VDD supplies for the PECL input buffer and the output buffer, allowing different voltages to be used. For example, the input clock could use a 3.3 V supply while the output operates from 2.5V. The device has an Output Enable pin that tri-states the clock output when the OE pin is taken low. The 508 is a member of IDT's ClockBlocksTM family.
支持社区
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qspi image 大于508k烧写问题
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2017年3月24日 -
求教从机端多字节接收问题
Hi, 我参考SDK里面的ble_app_peripheral中的user_svc1_led_wr_ind_handler部分，可以实现单字节数据的接收处理，请问对于手机主机端发过来的多字 ...
2020年3月2日
