5P49V5925

特性

5 LVCMOS outputs, including 1 reference output
In-system programmable with 4 independent output frequencies
Up to 200 MHz input/output frequencies
Also supports crystal input
Stores 4 different configurations in OTP non-volatile memory
< 100 mW core power (at 3.3V)
< 0.7 ps RMS phase jitter (typ)
Meets PCIe® Gen1/2/3, USB 3.0, 1/10 GbE clock requirements
1.8 / 2.5 / 3.3V core and output voltages
4x4 mm 24-ld VFQFPN
-40 °C to +85 °C operating temperature range
Supported by Timing Commander™ software tool

查找时钟生成的其他产品

5P49V5925 - Block Diagram

描述

The IDT 5P49V5925 is low-power programmable clock generator with best-in-class jitter performance and design flexibility with LVCMOS outputs capable of generating any output frequency. The 5P49V5925 is intended for high performance consumer, networking, industrial, computing, and data-communications applications. Configurations may be stored in on-chip One-Time Programmable (OTP) memory or changed using I²C interface. This is Renesas' fifth generation of programmable clock technology (VersaClock^® 5). The frequencies are generated from a single reference clock or crystal input. A glitchless manual switchover function allows one of the redundant clock inputs to be selected during normal operation.

Two select pins allow up to 4 different configurations to be programmed and accessible using processor GPIOs or bootstrapping. The different selections may be used for different operating modes (full function, partial function, partial power-down), regional standards (US, Japan, Europe) or system production margin testing. The device may be configured to use one of two I²C addresses to allow multiple devices to be used in a system.

此为出厂可配置设备。
试用自定义部件配置工具。

Part Number	Status	Samples	Stock	Package	Budgetary Price (USD)	Lead Count (#)	Carrier Type	Moisture Sensitivity Level (MSL)	Qty. per Reel (#)	Qty. per Carrier (#)	Pb (Lead) Free	Pb Free Category	Temp. Range (°C)	Country of Assembly	Country of Wafer Fabrication
5P49V5925A000NLGI	NRND	Available	Out of Stock	VFQFPN		24#	Tray	1	0	490#	Yes	e3 Sn	-40 to 85°C
5P49V5925A000NLGI8	NRND	N/A	Out of Stock	VFQFPN		24#	Reel	1	2500#	0	Yes	e3 Sn	-40 to 85°C
5P49V5925B000NLGI	NRND	Available	In Stock	VFQFPN	1ku \| $1.37	24#	Tray	1	0	490#	Yes	e3 Sn	-40 to 85°C	TAIWAN	SINGAPORE
5P49V5925B000NLGI8	NRND	N/A	In Stock	VFQFPN	1ku \| $1.37	24#	Reel	1	2500#	0	Yes	e3 Sn	-40 to 85°C	TAIWAN	SINGAPORE

加载中

筛选

数据手册 (1)

数据手册
英语
5P49V5925 Datasheet
RECOMMENDED
PDF 392 KB 7WDXRDKU4E7E-5-58032 2019年2月22日

手册和指南 (5)

手册 - 开发工具
英语
VersaClock 5 Family Register Descriptions and Programming Guide
PDF 1.25 MB 7WDXRDKU4E7E-5-57450 2023年2月02日
指南
英语
Timing Products for NXP (Freescale) i.MX
PDF 321 KB 7WDXRDKU4E7E-6-554 2018年11月01日
手册 - 开发工具
英语
VersaClock 5 Programmer Board User Guide
PDF 549 KB 7WDXRDKU4E7E-5-57217 2015年12月08日
手册 - 软件
英语
VersaClock 5 Timing Commander Users Guide
PDF 2.04 MB 7WDXRDKU4E7E-5-57026 2015年10月07日
手册 - 硬件
英语
VersaClock 5 Evaluation Board Users Guide
PDF 725 KB 7WDXRDKU4E7E-5-57025 2015年4月29日

应用说明和白皮书 (15)

应用说明
英语
PCB Layout Considerations for VersaClock Clock Generator Family
PDF 1.09 MB R31AN0026EU0102 Rev.1.02 2025年9月06日
应用说明
英语
Termination Options for High-Speed LVCMOS Driver Clock Drivers
PDF 187 KB R31AN0065EU0101 Rev.1.01 2023年11月14日
应用说明
英语
Timing Commander Installation Guide
PDF 348 KB R31AN0040EU0100 Rev.1.00 2023年3月10日
应用说明
英语
AN-1014 Microstrip vs Stripline: Crosstalk and RMS Phase Jitter
PDF 486 KB 7WDXRDKU4E7E-5-63374 2018年11月01日
应用说明
英语
AN-975 Cascading PLLs
PDF 255 KB 7WDXRDKU4E7E-5-61774 2017年8月02日

查看更多 (15)

产品通告（产品变更、EOL 等） (8)

产品变更通告
英语
PCN# : 220015 (R1) Add Alternate Assembly Location on VFQFPN Packages
PDF 734 KB 2022年11月16日
产品变更通告
英语
PCN# : 210023 Add Alternate Assembly Locations on Select VFQFN Packages
PDF 726 KB 2021年8月20日
产品变更通告
英语
PCN# : TB1912-02(R1) Convert Shipping Media from Tube or Tray to Cut Reel
PDF 5.71 MB 2020年6月09日
产品变更通告
英语
PCN# : A2005-01(R1) Add UTL, Thailand and JCET, China as Alternate Assembly Locations
PDF 725 KB 2020年6月09日
产品变更通告
英语
PCN# : TB1912-02 Convert Shipping Media from Tube or Tray to Cut Reel
PDF 5.61 MB 2020年1月08日

查看更多 (8)

原理图和设计文件 (2)

原理图
英语
VersaClock 5 Programmer Board Schematic
PDF 30 KB 7WDXRDKU4E7E-5-57802 2014年10月02日
原理图
英语
VersaClock 5 Evaluation Board Schematic
PDF 844 KB 7WDXRDKU4E7E-5-57024 2014年3月07日

营销资料 (1)

产品简述
英语
VersaClock 5 Programmable Clocks
PDF 469 KB 7WDXRDKU4E7E-6-8716 2014年12月09日

Renesas Boards & Kits

Programmable Clock Buffer Evaluation Board side view

EVKVC5-5901

Evaluation Board for 5P49V5901 VersaClock 5

This is the evaluation board for the Renesas 5P49V59xx VersaClock 5 family of programmable clock generators. With RMS phase jitter less than 0.7 picoseconds over the full 12 kHz to 20 MHz integration range, the device meets the stringent jitter requirements of PCI Express® Gen 1/2/3, USB 3.0,... 阅读详情

立即订购

加载中

This video provides an overview of the VersaClock 5 programmable clock generator family, including the 5P49V5901, 5P49V5913, 5P49V5914, 5P49V5923, 5P49V5925, 5P49V5927, 5P49V5929.

The VersaClock 5 family is an in-system programmable clock generator featuring up to four universal output pairs capable of producing independent frequencies up to 350 MHz configurable as HCSL, LVPECL, LVDS, or dual LVCMOS outputs. The highly integrated device consolidates four differential or eight single-ended clock generators and can store up to four different configuration settings, helping to minimize board space and bill-of-materials. Upon request, devices may be factory-programmed to the customer’s desired configuration.

Presented by Baljit Chandhoke, product line manager at IDT. Visit the Programmable Clocks page for more information.

Lab demonstration and clock jitter measurement showing VersaClock 5. The frequency analyzer shows phase jitter at approximately 575 picoseconds RMS. Presented by Baljit Chandhoke, product manager at IDT. For more information visit the Programmable Clocks page.

VersaClock® 5 is a low-power programmable clock generator with best-in-class jitter performance with less than 0.7psec RMS phase jitter from 12KHz to 20MHz. The highly integrated device consolidates four differential or eight single-ended clock generators and can store up to four different configuration settings, helping to minimize board space and bill-of-materials. The high-performance clock generator operates at less than 100mW core power (50 percent lower than competing devices), helping to ease system thermal constraints and reduce operating power expenses.

VersaClock 5 can take a crystal or a clock input. It has 4 fractional output dividers which allow the programming of 4 independent frequencies up to 350MHz. The four universal output pairs are independently configurable as HCSL, LVPECL, LVDS, or dual LVCMOS outputs. It also features a reference clock output. The fractional output dividers driving each output pair are easily programmed via I2C while the device is operating in the system, lending itself to system tuning and margin testing. Unlimited in-system reprogramming is possible via I2C, whereas four banks of one-time programmable non-volatile memory provide flexibility for multi-project inventory consolidation or design changes in field or production units. Upon request, devices may be factory-programmed to the customer's desired configuration.

Presented by Baljit Chandhoke, Product Marketing Manager at Integrated Device Technology, Inc.

This is a video introduction and demonstration of the VersaClock 5 Evaluation Board. This device uses Renesas's Timing Commander™ software platform, allowing engineers to configure and program their devices with an intuitive, time-saving graphical user interface (GUI).

The 5P49V5901 is an in-system programmable clock generator featuring four universal output pairs capable of producing independent frequencies up to 350 MHz in various output types. With RMS phase jitter less than 0.7 picoseconds over the full 12 kHz to 20 MHz integration range, the new device meets the stringent jitter requirements of PCI Express® Gen 1/2/3, USB 3.0, and 1G/10G Ethernet. The high-performance clock generator operates at less than 100 mW core power (50 percent lower than competing devices), helping to ease system thermal constraints, reduce operating power expenses, and maximize battery life.

The 5P49V5901's four universal output pairs are each independently configurable as HCSL, LVPECL, LVDS, or dual LVCMOS outputs. The fractional output dividers driving each output pair are easily programmed via I2C while the device is operating in the system, lending itself to system tuning and margin testing. Unlimited in-system reprogramming is possible via I2C, whereas four banks of one-time programmable non-volatile memory provide flexibility for multi-project inventory consolidation or design changes in field or production units. Upon request, devices may be factory-programmed to the customer's desired configuration.

Presented by Shudong Zheng, Sr. Design Engineer at IDT. For more information about Renesas's VersaClock 5, visit our VersaClock5 page.

Description

IDT's innovative support tool, Timing Commander™, expedites development cycles by empowering customers to program sophisticated timing devices with an intuitive and flexible Graphical User Interface. IDT's Timing Commander is a Windows™-based platform designed to serve user-friendly configuration interfaces, known as personalities, for various IDT products and product families. With a few simple clicks, the user is presented with a comprehensive, interactive block diagram offering the ability to modify desired input values, output values, and other configuration settings. The software automatically makes calculations, reports status monitors, and prepares register settings without the need to reference a datasheet. The tool also automatically loads the configuration settings over USB to an IDT evaluation board for immediate application in the circuit. Once the device has been configured and tuned for optimal system performance, the configuration file can be saved for factory-level programming before shipment. For more information about Timing Commander, visit our Timing Commander page.

Renesas's innovative support tool, Timing Commander™, expedites development cycles by empowering customers to program sophisticated timing devices with an intuitive and flexible Graphical User Interface. Renesas's Timing Commander is a Windows™-based platform designed to serve user-friendly configuration interfaces, known as personalities, for various Renesas products and product families. With a few simple clicks, the user is presented with a comprehensive, interactive block diagram offering the ability to modify desired input values, output values, and other configuration settings. The software automatically makes calculations, reports status monitors, and prepares register settings without the need to reference a datasheet. The tool also automatically loads the configuration settings over USB to an Renesas evaluation board for immediate application in the circuit. Once the device has been configured and tuned for optimal system performance, the configuration file can be saved for factory-level programming prior to shipment. Presented by Steven Gutierrez, Senior Product Application Engineer at Renesas.

Resources

Timing Commander

加载中加载中

Product Selector 微控制器和微处理器

中文

VersaClock 5 Low Power Programmable Clock Generator

特性

描述

筛选

当前筛选条件

推荐文档 (1)

数据手册 (1)

手册和指南 (5)

应用说明和白皮书 (15)

产品通告（产品变更、EOL 等） (8)

No Results Found.

No Results Found.

原理图和设计文件 (2)

No Results Found.

No Results Found.

No Results Found.

营销资料 (1)

No Results Found.

No Results Found.

Renesas Boards & Kits

Evaluation Board for 5P49V5901 VersaClock 5

筛选

当前筛选条件

软件与工具

按类型筛选

按供应商筛选

样例程序

按应用筛选

按功能筛选

按编译器筛选

按 IDE 筛选

模拟模型

Partner Solutions

No Results Found.

软件与工具 (5)

No Results Found.

模拟模型 (1)

No Results Found.

Resources