跳转到主要内容
瑞萨电子 (Renesas Electronics Corporation)

瑞萨电子的时序产品组合已被 SiTime 收购。

数据手册、文档以及样品订购仍将通过 Renesas.com 官网提供,直至 2026 年底。如需新设计、采购、技术支持以及产品咨询,请访问 SiTime.com 官网或发送电子邮件至 [email protected]。预计于 2026 年底前全面过渡至 SiTime。

特性

  • Input frequency:
  • For SONET non-FEC: 19.44MHz, 38.88MHz, 77.76MHz, 155.52MHz, 311.04MHz, or 622.08MHz
  • For SONET FEC: 20.83MHz, 41.66MHz, 83.31MHz, 166.63MHz, 333.26MHz, or 666.52MHz
  • For 10GE copper: 19.53MHz, 39.06MHz, 78.125MHz, 156.25MHz, 312.5MHz, or 625MHz
  • For 10GE optical: 20.14MHz, 40.28MHz, 80.56MHz, 161.13MHz, 322.26MHz, or 644.53MHz
  • Output frequency range selection
  • 1x, 2x, 4x, 8x, 16x, and 32x outputs on QOUT
  • Regenerated input clock on QREG
  • Lock indicator
  • Power-down mode
  • LVPECL or LVDS outputs
  • Two modes of output frequency range
  • Mode 0: QOUT range 155.5 - 166.6MHz. QREG is a regenerated version of the input clock.
  • Mode 1: QOUT range 622 - 666.5MHz. QREG is a regenerated version of the input clock frequency.
  • Hitless switchover
  • Differential LVPECL, LVDS, or single-ended LVTTL input interface
  • 2.375 - 3.465V core and I/O

描述

The 5T929 generates a high precision FEC (Forward Error Correction) or non-FEC source clock for SONET/SDH systems as well as a source clock for Gigabit Ethernet systems. This device also has clock regeneration capability: it creates a "clean" version of the clock input by using the internal oscillator to square the input clock's rising and falling edges and remove jitter. In the event that the main clock input fails, the device automatically locks to a backup reference clock using a hitless switchover mechanism. This device detects loss of valid CLKIN and leaves the VCO of the PLL at the last valid frequency while an alternate input REFIN is selected. If CLKIN and REFIN are different frequencies, the multiplication factor will be adjusted to retain the same output frequency. The 5T929 can act as a translator from a differential LVPECL, LVDS, or single-ended LVTTL input to LVPECL or LVDS outputs. The 5T929-10 has LVDS outputs and the 5T929-30 has LVPECL outputs. The two modes of output frequency range are controlled by the SELmode. When SELmode is high or low, the QOUT is a multiplied version of the input clock while QREG is a regenerated version of the input clock.

当前筛选条件