封装信息
| CAD 模型: | View CAD Model |
| Pkg. Type: | VFQFPN |
| Pkg. Code: | NDG48 |
| Lead Count (#): | 48 |
| Pkg. Dimensions (mm): | 6.0 x 6.0 x 0.9 |
| Pitch (mm): | 0.4 |
环境和出口类别
| Moisture Sensitivity Level (MSL) | 3 |
| Pb (Lead) Free | Yes |
| ECCN (US) | EAR99 |
| HTS (US) | 8542.39.0090 |
产品属性
| Lead Count (#) | 48 |
| Carrier Type | Reel |
| Moisture Sensitivity Level (MSL) | 3 |
| Qty. per Reel (#) | 2500 |
| Qty. per Carrier (#) | 0 |
| Pb (Lead) Free | Yes |
| Pb Free Category | e3 Sn |
| Temp. Range (°C) | -40 to 85°C |
| Accepts Spread Spec Input | Yes |
| Additive Phase Jitter Typ RMS (fs) | 100 |
| Additive Phase Jitter Typ RMS (ps) | 0.1 |
| Advanced Features | HW PLL mode control, Multiple SMBus addresses |
| App Jitter Compliance | PCIe Gen1, PCIe Gen2, PCIe Gen3 |
| Architecture | Common, SRNS |
| C-C Jitter Max P-P (ps) | 50 |
| Clock Spec. | PCIe Gen2, PCIe Gen3, PCIe Gen1 |
| Core Voltage (V) | 1.8 |
| Diff. Input Signaling | HCSL |
| Diff. Inputs | 1 |
| Diff. Output Signaling | LP-HCSL |
| Diff. Outputs | 8 |
| Diff. Termination Resistors | 0 |
| Feedback Input | No |
| I/O Voltage (V) | 1.05 - 1.8 |
| Input Freq (MHz) | 1 - 171.875 |
| Input Type | HCSL |
| Inputs (#) | 1 |
| Length (mm) | 6 |
| MOQ | 2500 |
| Output Banks (#) | 1 |
| Output Freq Range (MHz) | 1 - 171.875 |
| Output Signaling | LP-HCSL, HCSL |
| Output Skew (ps) | 50 |
| Output Type | LP-HCSL, HCSL |
| Output Voltage (V) | 0.8 |
| Outputs (#) | 8 |
| PLL | Yes |
| Package Area (mm²) | 36 |
| Phase Jitter Max RMS (ps) | 0.6 |
| Pitch (mm) | 0.4 |
| Pkg. Dimensions (mm) | 6.0 x 6.0 x 0.9 |
| Pkg. Type | VFQFPN |
| Power Consumption Typ (mW) | 62 |
| Product Category | Clock Buffers & Drivers, PCI Express Clocks |
| Prog. Clock | No |
| Reel Size (in) | 13 |
| Requires Terms and Conditions | Does not require acceptance of Terms and Conditions |
| Supply Voltage (V) | 1.05 - 1.8 |
| Tape & Reel | Yes |
| Thickness (mm) | 0.9 |
| Width (mm) | 6 |
有关 6P61033 的资源
描述
The 6P61033 is an 8-output very-low power buffer for 100MHz PCIe Gen 1, Gen 2, and Gen 3 applications with integrated output terminations providing Zo = 100Ω. The device has eight output enables for clock management and three selectable SMBus addresses.
