瑞萨电子 (Renesas Electronics Corporation)
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6V49205A Block Diagram
6V49205A Pin Diagram 48-pin TSSOP
6V49205A Pin Diagram 48-pin VFQFPN
3D illustration featuring top and bottom views of TSSOP IC chip package with 48 lead count.
6V49205A Block Diagram
6V49205A Pin Diagram 48-pin TSSOP
6V49205A Pin Diagram 48-pin VFQFPN
3D illustration featuring top and bottom views of TSSOP IC chip package with 48 lead count.

6V49205APAG

过时
Clock Generator for Freescale P10xx and P20xx System Clock with 66.66M DDR Clock
6V49205A Datasheet有关 6V49205A 的所有信息

封装信息

CAD 模型: View CAD Model
Pkg. Type: TSSOP
Pkg. Code: PAG48
Lead Count (#): 48
Pkg. Dimensions (mm): 12.5 x 6.1 x 1.0
Pitch (mm): 0.5

环境和出口类别

Moisture Sensitivity Level (MSL) 1
Pb (Lead) Free Yes
ECCN (US) EAR99
HTS (US) 8542.39.0090

产品属性

Lead Count (#) 48
Carrier Type Tube
Moisture Sensitivity Level (MSL) 1
Qty. per Carrier (#) 39
Package Area (mm²) 76.3
Pkg. Dimensions (mm) 12.5 x 6.1 x 1.0
Qty. per Reel (#) 0
Pb (Lead) Free Yes
Pb Free Category e3 Sn
Temp. Range (°C) 0 to 70°C
Advanced Features Programmable Clock, Spread Spectrum
App Jitter Compliance PCIe Gen1, PCIe Gen2, PCIe Gen3
C-C Jitter Max P-P (ps) 50
C-C Jitter Typ P-P (ps) 35
Chipset Manufacturer NXP
Chipset Name P1010, P1020, P2020, P2040
Core Voltage (V) 3.3V
Feedback Input No
Input Freq (MHz) 25 - 25
Input Type Crystal
Inputs (#) 1
Length (mm) 12.5
MOQ 156
Output Banks (#) 8
Output Freq Range (MHz) 100 - 100, 66.66 - 66.66, 80 - 80, 83.333 - 83.333, 12 - 12, 24 - 24, 125 - 125, 2.048 - 2.048, 25 - 25
Output Skew (ps) 50
Output Type LVCMOS, HCSL
Output Voltage (V) 3.3V
Outputs (#) 19
Period Jitter Max P-P (ps) 150
Period Jitter Typ P-P (ps) 96
Phase Jitter Max RMS (ps) 0.2
Phase Jitter Typ RMS (ps) 0.11
Pitch (mm) 0.5
Pkg. Type TSSOP
Prog. Clock Yes
Prog. Interface SMBUS
Reference Output No
Requires Terms and Conditions Does not require acceptance of Terms and Conditions
Spread Spectrum Yes
Tape & Reel No
Thickness (mm) 1
Width (mm) 6.1
已发布 No

描述

The 6V49205A is a main clock for Freescale P10xx and P20xx-based systems. It has a selectable system CCB clock and a 66.66MHz DDRCLK. The 6V49205A also provides LP-HCSL PCIe outputs for low power and reduced board space.

Output Features

  • 1 – Sys_CCB 3.3V LVCMOS output at 100M/83.33M/80M/66.66M
  • 1 – DDRCLK 3.3V LVCMOS output at 66.66M
  • 1 –125M 3.3V LVCMOS output
  • 6 – LP-HCSL PCIe pairs selectable at 100M or 125M
  • 6 – 25MHz 3.3V LVCMOS outputs
  • 2 – 2.048M 3.3V LVCMOS outputs
  • 2 – USB 3.3V LVCMOS outputs at 12M or 24M
有关 6V49205A 的所有信息