跳转到主要内容

概览

描述

The 70V659 is a high-speed 128K x 36 asynchronous dual-port static RAM designed to be used as a stand-alone dual-port RAM or as a combination Master/Slave dual-port RAM for a 72-bit or more word system. Using the Master/Slave dual-port RAM approach in 72-bit or wider memory system applications results in full-speed, error-free operation without the need for additional discrete logic. An automatic power-down feature controlled by the chip enables (either CE0 or CE1) permits the on-chip circuitry of each port to enter a very low standby power mode.

特性

  • Dual-port allows simultaneous access of the same memory location
  • Dual chip enables allow for depth expansion without external logic
  • Easily expands data bus width to 72 bits or more using the Master/Slave select when cascading more than one device
  • Busy and Interrupt flags
  • On-chip port arbitration logic
  • Full on-chip hardware support of semaphore signaling between ports; fully asynchronous operation from either port
  • Separate byte controls for multiplexed bus and bus-matching compatibility
  • Includes JTAG functionality on BGA package versions only
  • LVTTL-compatible, single 3.3V (±150mV) power supply for core
  • LVTTL-compatible, selectable 3.3V (±150mV)/2.5V (±100mV) power supply for I/Os and control signals on each port
  • Available in a 208-pin PQFP, 208-ball fpBGA, and 256-ball BGA
  • Industrial temperature range (–40 °C to +85 °C) is available

产品对比

应用

文档

设计和开发

模型

ECAD 模块

点击产品选项表中的 CAD 模型链接,查找 SamacSys 中的原理图符号、PCB 焊盘布局和 3D CAD 模型。如果符号和模型不可用,可直接在 SamacSys 请求该符号或模型。

Diagram of ECAD Models

模型

类型 文档标题 日期
模型 - VHDL ZIP 5 KB
模型 - IBIS ZIP 51 KB
模型 - BSDL ZIP 9 KB
模型 - Verilog ZIP 11 KB
4 items

产品选项

当前筛选条件