封装信息
| Lead Count (#) | 208 |
| Pkg. Code | DR208 |
| Pitch (mm) | 0.5 |
| Pkg. Type | PQFP |
| Pkg. Dimensions (mm) | 28.0 x 28.0 x 3.5 |
环境和出口类别
| Pb (Lead) Free | No |
| Moisture Sensitivity Level (MSL) | 3 |
| ECCN (US) | NLR |
| HTS (US) | 8542320041 |
产品属性
| Lead Count (#) | 208 |
| Pb (Lead) Free | No |
| Carrier Type | Tray |
| Moisture Sensitivity Level (MSL) | 3 |
| Access Time (ns) | 12 |
| Architecture | Dual-Port |
| Bus Width (bits) | 36 |
| Core Voltage (V) | 3.3 |
| Density (Kb) | 4608 |
| Function | Busy, Interrupt, JTAG, Master, Semaphore, Slave |
| I/O Type | 3.3 V LVTTL |
| Interface | Async |
| Length (mm) | 28 |
| MOQ | 24 |
| Organization | 128K x 36 |
| Package Area (mm²) | 784.0 |
| Pb Free Category | e0 |
| Pitch (mm) | 0.5 |
| Pkg. Dimensions (mm) | 28.0 x 28.0 x 3.5 |
| Pkg. Type | PQFP |
| Qty. per Carrier (#) | 24 |
| Qty. per Reel (#) | 0 |
| Requires Terms and Conditions | Does not require acceptance of Terms and Conditions |
| Tape & Reel | No |
| Temp. Range | 0 to 70°C |
| Thickness (mm) | 3.5 |
| Width (mm) | 28 |
描述
The 70V659 is a high-speed 128K x 36 asynchronous dual-port static RAM designed to be used as a stand-alone dual-port RAM or as a combination Master/Slave dual-port RAM for a 72-bit or more word system. Using the Master/Slave dual-port RAM approach in 72-bit or wider memory system applications results in full-speed, error-free operation without the need for additional discrete logic. An automatic power-down feature controlled by the chip enables (either CE0 or CE1) permits the on-chip circuitry of each port to enter a very low standby power mode.