概览
描述
The 71124 5V CMOS SRAM is organized as 128K x 8. The JEDEC centerpower/GND pinout reduces noise generation and improves system performance. All bidirectional inputs and outputs of the 71124 are TTL-compatible and operation is from a single 5V supply. Fully static asynchronous circuitry is used; no clocks or refreshes are required for operation.
特性
- JEDEC revolutionary pinout (center power/GND) for reduced noise.
- Equal access and cycle times – Commercial and Industrial: 12/15/20ns
- One Chip Select plus one Output Enable pin
- Bidirectional inputs and outputs directly TTL-compatible
- Low power consumption via chip deselect
- Available in a 32-pin 400 mil Plastic SOJ packages
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| 类型 | 文档标题 | 日期 |
| 数据手册 | PDF 87 KB | |
| 指南 | PDF 207 KB 日本語 | |
| EOL 通告 | PDF 1.17 MB | |
| 指南 | PDF 1.27 MB 日本語 | |
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