瑞萨电子 (Renesas Electronics Corporation)
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71V3556

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3.3V 128Kx36 ZBT Synchronous Pipelined SRAM with 3.3V I/O

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概览

The 71V3556 3.3V CMOS synchronous SRAM, organized as 128K x 36, is designed to eliminate dead bus cycles when turning the bus around between reads and writes or writes and reads. Thus, it has been given the name ZBT™, or Zero Bus Turnaround. The 71V3556 contains data I/O, address, and control signal registers.

71V3556 - Block Diagram
71V3556 - Block Diagram
  • High-performance system speed 200MHz (x18) (3.2ns Clock-to-Data access)
  • ZBT feature - No dead cycles between write and read cycles
  • Internally synchronized output buffer enable eliminates the need to control OE
  • Single R/W (Read/Write) control pin
  • Positive clock-edge triggered address, data, and control signal registers for fully pipelined applications
  • 4-word burst capability (interleaved or linear)
  • Individual byte write (BW1 - BW4) control (May tie active)
  • Three chip enables for simple depth expansion
  • 3.3V power supply (±5%), 3.3V I/O supply (VDDQ)
  • Optional- Boundary Scan JTAG interface (IEEE 1149.1 compliant)
  • Available in 100-pin TQFP, 119-pin BGA, and 165 fpBGA packages

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模型
类型 文档标题 日期
模型 - IBIS
71v3556_BG IBIS Model
ZIP 9 KB
模型 - IBIS
71V3556_PF IBIS Model
ZIP 9 KB
模型 - Verilog
71V3556 Verilog Model
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