特性
- Functionally compatible with the 72V255/65/75/85 SuperSync FIFOs
- Up to 166 MHz Operation of the Clocks
- User selectable Asynchronous read and/or write ports (BGA Only)
- User selectable input and output port bus sizing
- Pin to Pin compatible to the higher density 72V2x3/72V21x3 devices
- 5V tolerant inputs
- Auto power down minimizes standby power consumption
- Master Reset clears entire FIFO
- Partial Reset clears data, but retains programmable settings
- Easily expandable in depth and width
- JTAG port, provided for Boundary Scan function (BGA Only)
- Independent Read and Write Clocks
- Available in a 80-pin TQFP and 100-pin BGA packages
- Industrial temperature range (–40C to +85C) is available
72V233 - Block Diagram
描述
The 72V233 2K x 9/1K x 18 SuperSync II FIFO memory has flexible x9/x18 Bus-Matching on both read and write ports. The variable clock cycle counting delay associated with the latency period found on previous SuperSync devices has been eliminated. SuperSync II FIFOs are appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match buses of unequal sizes.
