封装信息
| CAD 模型: | View CAD Model |
| Pkg. Type: | TQFP |
| Pkg. Code: | EDG64 |
| Lead Count (#): | 64 |
| Pkg. Dimensions (mm): | 10.0 x 10.0 x 1.0 |
| Pitch (mm): | 0.5 |
环境和出口类别
| Moisture Sensitivity Level (MSL) | 3 |
| Pb (Lead) Free | Yes |
| ECCN (US) | EAR99 |
| HTS (US) | 8542.39.0090 |
产品属性
| Lead Count (#) | 64 |
| Carrier Type | Tray |
| Moisture Sensitivity Level (MSL) | 3 |
| Qty. per Reel (#) | 0 |
| Qty. per Carrier (#) | 160 |
| Pb (Lead) Free | Yes |
| Pb Free Category | e3 Sn |
| Temp. Range (°C) | -40 to 85°C |
| Abs. Pull Range Min. (± PPM) | 50 |
| Advanced Features | PLL-based Synchronous Clock |
| Core Voltage (V) | 3.3 |
| Feedback Input | No |
| Input Freq (MHz) | 10 - 10, 12.88 - 12.88, 15 - 15, 15.36 - 15.36, 20 - 20, 30.72 - 30.72, 61.44 - 61.44, 122.88 - 122.88 |
| Input Type | LVDS, LVPECL, LVHSTL |
| Inputs (#) | 2 |
| Length (mm) | 10 |
| Loop Bandwidth Range (Hz) | 8.5 - 22200 |
| MOQ | 160 |
| Output Banks (#) | 3 |
| Output Freq Range (MHz) | 30.72 - 30.72, 38.4 - 38.4, 61.44 - 61.44, 76.8 - 76.8, 98.304 - 98.304, 122.88 - 122.88, 153.6 - 153.6, 245.76 - 245.76, 307.2 - 307.2, 491.52 - 491.52, 614.4 - 614.4 |
| Output Skew (ps) | 200 |
| Output Type | LVPECL |
| Output Voltage (V) | 3.3 |
| Outputs (#) | 9 |
| Package Area (mm²) | 100 |
| Period Jitter Max P-P (ps) | 30 |
| Phase Jitter Typ RMS (ps) | 0.92 |
| Pitch (mm) | 0.5 |
| Pkg. Dimensions (mm) | 10.0 x 10.0 x 1.0 |
| Pkg. Type | TQFP |
| Product Category | Jitter Attenuators |
| Prog. Clock | No |
| Requires Terms and Conditions | Does not require acceptance of Terms and Conditions |
| Tape & Reel | No |
| Thickness (mm) | 1 |
| Width (mm) | 10 |
| Xtal Freq (KHz) | 30720 - 30720 |
有关 813078I 的资源
描述
The 813078I is a PLL-based synchronous clock solution that is optimized for wireless infrastructure equipment where frequency translation and jitter attenuation are needed. The device contains two internal PLL stages that are cascaded in series. The first PLL stage attenuates the reference clock jitter by using an internal or external VCXO circuit. The internal VCXO requires the connection of an external inexpensive pullable crystal (XTAL) to the 813078I. This first PLL stage (VCXO PLL) uses external passive loop filter components which are used to optimize the PLL loop bandwidth and damping characteristics for the given application. The output of the first stage VCXO PLL is a stable and jitter-tolerant 30.72MHz reference input for the second PLL stage. The second PLL stage provides frequency translation by multiplying the output of the first stage up to 491.52MHz or 614.4MHz. The low phase noise characteristics of the VCXO-PLL clock signal are maintained by the internal FemtoClock® PLL, which requires no external components or complex programming. Two independently configurable frequency dividers translate the internal VCO signal to the desired output frequencies. All frequency translation ratios are set by device configuration pins. Supported input reference clock frequencies: 10MHz, 12.8MHz, 15MHz, 15.36MHz, 20MHz, 30.72MHz, 61.44MHz, and 122.88MHz Supported output clock frequencies: 30.72MHz, 38.4MHz, 61.44MHz, 76.8MHz, 122.88MHz, 153.6MHz, 245.76MHz, 491.52MHz, and 614.4MHz