封装信息
| CAD 模型: | View CAD Model |
| Pkg. Type: | CABGA |
| Pkg. Code: | BAG144 |
| Lead Count (#): | 144 |
| Pkg. Dimensions (mm): | 13.0 x 13.0 x 1.53 |
| Pitch (mm): | 1 |
环境和出口类别
| Moisture Sensitivity Level (MSL) | 3 |
| Pb (Lead) Free | Yes |
| ECCN (US) | EAR99 |
| HTS (US) | 8542.39.0090 |
产品属性
| Lead Count (#) | 144 |
| Carrier Type | Reel |
| Moisture Sensitivity Level (MSL) | 3 |
| Qty. per Reel (#) | 1000 |
| Qty. per Carrier (#) | 0 |
| Pb (Lead) Free | Yes |
| Pb Free Category | e1 SnAgCu |
| Temp. Range (°C) | -40 to 85°C |
| Advanced Features | Hitless Reference Switching, Fractional-N Input Dividers, External Sync Input, External Feedback, VCXO-based APLL, LOS Inputs |
| Application | Port Synchronizer |
| Channels (#) | 3 |
| Core Voltage (V) | 1.8 |
| Diff. Inputs | 6 |
| Diff. Outputs | 6 |
| Input Freq (MHz) | 1.0E-6 - 650 |
| Input Freq Range Type | TDM, DS1, E1, SONET/SDH, Ethernet, OTN, Sync Pulse |
| Input Type | LVCMOS, LVPECL, LVDS |
| Inputs (#) | 12 |
| Length (mm) | 13 |
| MOQ | 1000 |
| Output Freq Range (MHz) | 1.0E-6 - 650 |
| Output Freq Range Type | 1PPS (1 Hz), TDM, DS1, E1, DS2, E3, DS3, 100BASE-T, STM-1/OC-3, STM-4/OC-12, 1000BASE-T/X, STM-16/OC-48, STM-64/OC-192/10GBASE-W, 10GBASE-R, XGMII/XAUI |
| Output Type | LVCMOS, LVPECL, LVDS |
| Outputs (#) | 13 |
| Package Area (mm²) | 169 |
| Phase Jitter Typ RMS (ps) | 0.23 |
| Pitch (mm) | 1 |
| Pkg. Dimensions (mm) | 13.0 x 13.0 x 1.53 |
| Pkg. Type | CABGA |
| Reel Size (in) | 13 |
| Requires Terms and Conditions | Does not require acceptance of Terms and Conditions |
| Tape & Reel | Yes |
| Thickness (mm) | 1.53 |
| Width (mm) | 13 |
| 已发布 | No |
有关 82P33741 的资源
描述
The 82P33741 Port Synchronizer for IEEE 1588 and 10G/40G Synchronous Ethernet provides tools to manage timing references, clock conversion and timing paths for IEEE 1588 and Synchronous Ethernet (SyncE). The device supports up to three independent timing paths for: IEEE 1588 clock generation; SyncE clock generation; and general purpose frequency translation. The device outputs low-jitter clocks that can directly synchronize 40GBASE-R, 10GBASE-R and 10GBASE-W and lower-rate Ethernet interfaces; as well as CPRI/OBSAI, SONET/SDH and PDH interfaces and IEEE 1588 Time Stamp Units (TSUs).
► Download the Altera and IDT Synchronous Ethernet Solution for ITU-T G.8262 white paper