特性
- Six selectable 100MHz, 125MHz, 156.25MHz and 312.5MHz
clocks for sRIO, XAUI, SGMII and HCSL interface levels - One 125MHz RGMII clock (QG), LVCMOS/LVTTL interface levels
- One 50MHz processor core clock (QF), LVCMOS/LVTTL interface levels
- Two 25MHz QREF clocks, LVCMOS/LVTTL interface levels, 15Ω output impedance
- Selectable external crystal or differential (single-ended) input source
- Crystal oscillator interface designed for 25MHz, parallel resonant crystal
- Differential CLK, nCLK input pair that can accept: LVPECL, LVDS, LVHSTL, HCSL input levels
- Internal resistor bias on nCLK pin allows the user to drive CLK input with external single-ended (LVCMOS/ LVTTL) input levels
- Full 3.3V or mixed 3.3V core/2.5V output supply modes, (RGMII output and QREF outputs)
- Full 3.3V output supply mode, (HCSL and core clock outputs)
- -40 °C to 85 °C ambient operating temperature
- Lead-free (RoHS 6) packaging
8413S08I - Block Diagram
描述
The 8413S06 is a PLL-based clock generator specifically designed for Cavium Networks Octeon II processors. This high-performance device is optimized to generate the processor core reference clock, sRIO, XAUI, SGMII SerDes reference clocks and the clocks for both the Gigabit Ethernet MAC and PHY. The clock generator offers ultra-low jitter, low-skew clock outputs, and edge rates that easily meet the input requirements for the CN63XX and CN68XX series of processors. The output frequencies are generated from a 25MHz external input source or an external 25MHz parallel resonant crystal.The industrial temperature range of the 8413S06 supports telecommunication, networking, and storage requirements.
应用
- Systems using Cavium Processors
- CPE Gateway Design
- Home Media Servers
- 802.11n AP or Gateway
- Soho Secure Gateway
- Soho SME Gateway
- Wireless Soho and SME VPN Solutions
- Wired and Wireless Network Security
- Web Servers and Exchange Servers
