封装信息
| CAD 模型: | View CAD Model |
| Pkg. Type: | SOIC |
| Pkg. Code: | DCG8 |
| Lead Count (#): | 8 |
| Pkg. Dimensions (mm): | 4.9 x 3.9 x 1.5 |
| Pitch (mm): | 1.27 |
环境和出口类别
| Moisture Sensitivity Level (MSL) | 1 |
| Pb (Lead) Free | Yes |
| ECCN (US) | EAR99 |
| HTS (US) | 8542.39.0090 |
产品属性
| Lead Count (#) | 8 |
| Carrier Type | Reel |
| Moisture Sensitivity Level (MSL) | 1 |
| Output Freq Range (MHz) | 150 - 150 |
| Qty. per Reel (#) | 3000 |
| Qty. per Carrier (#) | 0 |
| Pb (Lead) Free | Yes |
| Pb Free Category | e3 Sn |
| Temp. Range (°C) | 0 to 70°C |
| Advanced Features | Spread Spectrum |
| Core Voltage (V) | 2.5V, 3.3V |
| Feedback Input | No |
| Input Freq (MHz) | 25 - 25 |
| Input Type | Crystal |
| Inputs (#) | 1 |
| Length (mm) | 4.9 |
| MOQ | 3000 |
| Output Banks (#) | 1 |
| Output Type | LVPECL |
| Output Voltage (V) | 2.5V, 3.3V |
| Outputs (#) | 1 |
| Package Area (mm²) | 19.1 |
| Phase Jitter Typ RMS (ps) | 0.64 |
| Pitch (mm) | 1.27 |
| Pkg. Dimensions (mm) | 4.9 x 3.9 x 1.5 |
| Pkg. Type | SOIC |
| Prog. Clock | No |
| Reel Size (in) | 13 |
| Reference Output | No |
| Requires Terms and Conditions | Does not require acceptance of Terms and Conditions |
| Spread Spectrum | Yes |
| Tape & Reel | Yes |
| Thickness (mm) | 1.5 |
| Width (mm) | 3.9 |
| 已发布 | No |
有关 843241 的资源
描述
The 843241 is a low jitter, high performance clock generator and a member of the FemtoClock® family of silicon timing products. The 843241 is designed for use in the SAS-2 interconnect and the three transport protocols that use the SAS-2 interconnect: Serial SCSI Protocol (SSP), Serial ATA Tunneled Protocol (STP), and Serial Management Protocol (SMP). The 843241 has excellent (<1ps) RMS phase jitter, over the SAS defined integration range. The 843241 uses an external, 25MHz, parallel resonant crystal to generate three selectable output frequencies: 75MHz, 100MHz, 150MHz, and 300MHz. This silicon based approach provides excellent frequency stability and reliability. The 843241 features up, down, and center spread spectrum (SSC) clocking techniques. The up, down and center SSC will be required in the SAS-2 applications that have three clock trees in the HBA and expander ASICs (see Applications Information section, Figure 3).