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瑞萨电子 (Renesas Electronics Corporation)
Differential-to-LVDS Fanout Buffer W/Divider And Glitchless Switch

封装信息

CAD 模型:View CAD Model
Pkg. Type:PTQFP
Pkg. Code:DXG48
Lead Count (#):48
Pkg. Dimensions (mm):7.0 x 7.0 x 1.0
Pitch (mm):0.5

环境和出口类别

Moisture Sensitivity Level (MSL)3
Pb (Lead) FreeYes
ECCN (US)EAR99
HTS (US)8542.39.0090

产品属性

Lead Count (#)48
Carrier TypeTray
Moisture Sensitivity Level (MSL)3
Qty. per Reel (#)0
Qty. per Carrier (#)250
Pb (Lead) FreeYes
Pb Free Categorye3 Sn
Temp. Range (°C)-40 to 85°C
Adjustable PhaseNo
Advanced FeaturesIndividual output enable, Glitchless input switch
Channels (#)1
Core Voltage (V)2.5V, 3.3V
Divider Value1, 2
FunctionBuffer, Multiplexer
Input Freq (MHz)1500
Input TypeHCSL, LVDS, LVPECL
Inputs (#)2
Length (mm)7
MOQ250
Output Banks (#)2
Output Freq Range (MHz)1500, 750
Output Skew (ps)40
Output TypeLVDS
Output Voltage (V)2.5V, 3.3V
Outputs (#)8
Package Area (mm²)49
Pitch (mm)0.5
Pkg. Dimensions (mm)7.0 x 7.0 x 1.0
Pkg. TypePTQFP
Product CategoryClock Buffers & Drivers, Clock Multiplexers, RF Buffers
Requires Terms and ConditionsDoes not require acceptance of Terms and Conditions
Supply Voltage (V)2.5 - 2.5, 3.3 - 3.3
Tape & ReelNo
Thickness (mm)1
Width (mm)7

描述

The 854S1208I is a low skew, 8 output LVDS Fanout Buffer with selectable divider. The 854S1208I has 2 selectable inputs that accept a variety of differential input types. The device provides the capability to suppress any glitch at the outputs of the device during an input clock switch to enhance clock redundancy in fault tolerant applications. The divide select inputs, DIV_SELA and DIV_SELB, control the output frequency of each bank. The output banks can be independently selected for ÷1 or ÷2 operation. The output enable pins assigned to each output, support enabling and disabling each output individually. The 854S1208I is characterized at full 3.3V or 2.5V output operating supply modes. Guaranteed output and part-to-part skew characteristics make the 854S1208I ideal for high performance applications.