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1-to-3 Differential-to-3.3V LVPECL Zero Delay Buffer

封装信息

Pkg. Type:SSOP
Pkg. Code:PYG28
Lead Count (#):28
Pkg. Dimensions (mm):10.2 x 5.3 x 1.73
Pitch (mm):0.65

环境和出口类别

Pb (Lead) FreeYes
Moisture Sensitivity Level (MSL)1
ECCN (US)
HTS (US)

产品属性

Pkg. TypeSSOP
Lead Count (#)28
Pb (Lead) FreeYes
Carrier TypeReel
Advanced FeaturesFeedback Input
C-C Jitter Max P-P (ps)25
Core Voltage (V)3.3
Feedback InputYes
Input Freq (MHz)31.25 - 700
Input TypeHCSL, HSTL, LVDS, LVPECL, SSTL
Inputs (#)2
Length (mm)10.2
MOQ1000
Moisture Sensitivity Level (MSL)1
Output Banks (#)1
Output Freq Range (MHz)31.25 - 700
Output Skew (ps)25
Output TypeLVPECL
Output Voltage (V)3.3
Outputs (#)3
Package Area (mm²)54.1
Pb Free Categorye3 Sn
Phase Jitter Max RMS (ps)50
Pitch (mm)0.65
Pkg. Dimensions (mm)10.2 x 5.3 x 1.73
Prog. ClockNo
Qty. per Carrier (#)0
Qty. per Reel (#)1500
Reel Size (in)13
Requires Terms and ConditionsDoes not require acceptance of Terms and Conditions
Tape & ReelYes
Temp. Range (°C)0 to 70°C
Thickness (mm)1.73
Width (mm)5.3

描述

The 8633-01 is a high performance 1-to-3 Differential-to-3.3V LVPECL Zero Delay Buffer. The 8633-01 has two selectable clock inputs. The CLKx, nCLKx pairs can accept most standard differential input levels. Utilizing one of the outputs as feedback to the PLL, output frequencies up to 700MHz can be regenerated with zero delay with respect to the input. Dual reference clock inputs support redundant clock or multiple reference applications.