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Low Skew,÷1/÷2 Differential-to- 3.3V LVPECL Clock Generator

封装信息

CAD 模型:View CAD Model
Pkg. Type:TSSOP
Pkg. Code:PGG20
Lead Count (#):20
Pkg. Dimensions (mm):6.5 x 4.4 x 1.0
Pitch (mm):0.65

环境和出口类别

Moisture Sensitivity Level (MSL)1
Pb (Lead) FreeYes
ECCN (US)EAR99
HTS (US)8542.39.0090

产品属性

Lead Count (#)20
Carrier TypeReel
Moisture Sensitivity Level (MSL)1
Qty. per Reel (#)3000
Qty. per Carrier (#)0
Pb (Lead) FreeYes
Pb Free Categorye3 Sn
Temp. Range (°C)0 to 70°C
Additive Phase Jitter Typ RMS (fs)40
Additive Phase Jitter Typ RMS (ps)0.04
Core Voltage (V)3.3
Divider Value1, 2
FunctionBuffer, Multiplexer, Divider
Input Freq (MHz)650
Input TypeCML, HCSL, HSTL, LVDS, LVPECL, SSTL
Inputs (#)2
Length (mm)6.5
MOQ3000
Output Banks (#)2
Output Freq Range (MHz)650
Output Skew (ps)60
Output TypeLVPECL
Output Voltage (V)3.3
Outputs (#)4
Package Area (mm²)28.6
Pitch (mm)0.65
Pkg. Dimensions (mm)6.5 x 4.4 x 1.0
Pkg. TypeTSSOP
Reel Size (in)13
Requires Terms and ConditionsDoes not require acceptance of Terms and Conditions
Tape & ReelYes
Thickness (mm)1
Width (mm)4.4
已发布No

描述

The 8737-11 is a low skew, high performance Differential-to-3.3V LVPECL Clock Generator/Divider. The 8737-11 has two selectable clock inputs. The CLK, nCLK pair can accept most standard differential input levels. The PCLK, nPCLK pair can accept LVPECL, CML, or SSTL input levels. The clock enable is internally synchronized to eliminate runt pulses on the outputs during asynchronous assertion/deassertion of the clock enable pin. Guaranteed output and part-to-part skew characteristics make the 8737-11 ideal for clock distribution applications demanding well defined performance and repeatability.