跳转到主要内容
瑞萨电子 (Renesas Electronics Corporation) - June is Pride Month, a month to raise awareness of the rights and the culture of the LGBTQ+ community

特性

  • Fully integrated PLL
  • Fourteen LVCMOS/LVTTL outputs to include: twelve clocks, one feedback, one sync
  • Selectable differential CLK, nCLK inputs or LVCMOS/LVTTL reference clock inputs
  • CLK0, CLK1 can accept the following input levels: LVCMOS or LVTTL
  • CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL
  • Output frequency range: 10MHz to 150MHz
  • VCO range: 240MHz to 500MHz
  • Output skew: 200ps (maximum)
  • Cycle-to-cycle jitter, (all banks ÷4): 55ps (maximum)
  • Full 3.3V supply voltage
  • -40°C to 85°C ambient operating temperature
  • Compatible with PowerPC™ and Pentium™ Microprocessors
  • Available in both standard (RoHS 5) and lead-free (RoHS 6) packages

描述

The 87973I-147 is a LVCMOS/LVTTL clock generator and a member of the HiPerClockS™ family of High Performance Clock Solutions from IDT. The 87973I-147 has three selectable inputs and provides 14 LVCMOS/LVTTL outputs. The 87973I-147 is a highly flexible device. The three selectable inputs (1 differential and 2 single ended inputs) are often used in systems requiring redundant clock sources. Up to three different output frequencies can be generated among the three output banks. The three output banks and feedback output each have their own output dividers which allows the device to generate a multitude of different bank frequency ratios and output-to-input frequency ratios. In addition, 2 outputs in Bank C (QC2, QC3) can be selected to be inverting or non-inverting. The output frequency range is 10MHz to 150MHz. The input frequency range is 6MHz to 120MHz. The 87973I-147 also has a QSYNC output which can be used for system synchronization purposes. It monitors Bank A and Bank C outputs and goes low one period prior to coincident rising edges of Bank A and Bank C clocks. QSYNC then goes high again when the coincident rising edges of Bank A and Bank C occur. This feature is used primarily in applications where Bank A and Bank C are running at different frequencies, and is particularly useful when they are running at non-integer multiples of one another.

Part NumberStatusSamplesStockPackageLead Count (#)Carrier TypeMoisture Sensitivity Level (MSL)Qty. per Reel (#)Qty. per Carrier (#)Pb (Lead) FreePb Free CategoryTemp. Range (°C)
87973DYI-147LFObsoleteN/AIn StockTQFP52#Tray30160#Yese3 Sn-40 to 85°C
87973DYI-147LFTObsoleteN/AOut of StockTQFP52#Reel3500#0Yese3 Sn-40 to 85°C
支持社区

支持社区

在线询问瑞萨电子工程社群的技术人员,快速获得技术支持。
浏览文章

知识库

浏览我们的知识库,获取文章、常见问题解答及其他实用资源。
提交工单

提交工单

需要咨询技术性问题或提供非公开信息吗?