跳转到主要内容

概览

描述

The 8R9306I 2.5V differential clock buffer is a user-selectable differential input to six LVDS outputs. The fanout from a differential input to six LVDS outputs reduces loading on the preceding driver and provides an efficient clock distribution network. The 8R9306I can act as a translator from a differential HSTL, eHSTL, LVPECL (2.5V), LVPECL (3.3V), CML, or LVDS input to LVDS outputs. A single-ended 3.3V, 2.5V LVTTL input can also be used to translate to LVDS outputs. The redundant input capability allows for an asynchronous change-over from a primary clock source to a secondary clock source. Selectable reference inputs are controlled by SEL. The 8R9306I outputs can be asynchronously enabled/disabled. When disabled, the outputs will drive to the value selected by the GL pin. Multiple power and grounds reduce noise.

特性

  • Guaranteed low skew: 40ps (maximum)
  • Very low duty cycle distortion: < 125ps (maximum)
  • High speed propagation delay: < 1.75ns (maximum)
  • Up to 1GHz operation
  • Selectable inputs
  • Hot insertable and overvoltage tolerant inputs
  • 3.3V/2.5V LVTTL, HSTL eHSTL, LVPECL (2.5V), LVPECL (3.3V), CML or LVDS input interface
  • Selectable differential inputs to six LVDS outputs
  • Power-down mode
  • 2.5V VDD
  • -40 °C to 85 °C ambient operating temperature
  • Available in a VFQFPN package

产品对比

应用

文档

设计和开发

模型

ECAD 模块

点击产品选项表中的 CAD 模型链接,查找 SamacSys 中的原理图符号、PCB 焊盘布局和 3D CAD 模型。如果符号和模型不可用,可直接在 SamacSys 请求该符号或模型。

Diagram of ECAD Models

产品选项

当前筛选条件

支持

支持社区

支持社区

在线询问瑞萨电子工程社群的技术人员,快速获得技术支持。
浏览常见问题解答

常见问题

浏览我们的知识库,了解常见问题的解答。
提交工单

提交工单

需要咨询技术性问题或提供非公开信息吗?