特性
- Four low skew, low additive jitter LVDS output pairs
- Two selectable differential clock input pairs
- Differential PCLKx, nPCLKx pairs can accept the following differential input levels: LVDS, LVPECL
- Maximum input clock frequency: 2GHz
- LVCMOS/LVTTL interface levels for the control input select pin
- Output skew: 20ps (maximum)
- Propagation delay: 310ps (maximum)
- Low additive phase jitter, RMS; fREF = 156.25MHz, VPP = 1V, 10kHz - 20MHz: 100fs (maximum)
- Full 3.3V supply voltage
- Lead-free (RoHS 6), 16-Lead VFQFN packaging
- -40°C to 85°C ambient operating temperature
描述
The IDT8SLVD1204-33I is a high-performance differential LVDS fanout buffer. The device is designed for the fanout of high-frequency, very low additive phase-noise clock and data signals. The IDT8SLVD1204-33I is characterized to operate from a 3.3V power supply. Guaranteed output-to-output and part-to-part skew characteristics make the IDT8SLVD1204-33I ideal for those clock distribution applications demanding well-defined performance and repeatability. Two selectable differential inputs and four low skew outputs are available. The integrated bias voltage reference enables easy interfacing of single-ended signals to the device inputs. The device is optimized for low power consumption and low additive phase noise.
For a 2.5 V version of this device, please refer to the 8SLVD1204I.
产品参数
| 属性 | 值 |
|---|---|
| Temp. Range (°C) | -40 to 85°C |
| Product Category | Clock Buffers & Drivers, Clock Multiplexers, RF Buffers |
封装选项
| Pkg. Type | Pkg. Dimensions (mm) | Lead Count (#) | Pitch (mm) |
|---|---|---|---|
| VFQFPN | 3.0 x 3.0 x 1.0 | 16 | 0.5 |