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Crystal or Differential to Differential Clock Fanout Buffer

封装信息

CAD 模型:View CAD Model
Pkg. Type:VFQFPN
Pkg. Code:NLG32
Lead Count (#):32
Pkg. Dimensions (mm):5.0 x 5.0 x 0.9
Pitch (mm):0.5

环境和出口类别

Moisture Sensitivity Level (MSL)3
Pb (Lead) FreeYes
ECCN (US)EAR99
HTS (US)8542.39.0090

产品属性

Lead Count (#)32
Carrier TypeTray
Moisture Sensitivity Level (MSL)3
Qty. per Reel (#)0
Qty. per Carrier (#)490
Pb (Lead) FreeYes
Pb Free Categorye3 Sn
Temp. Range (°C)-40 to 85°C
Country of AssemblyTAIWAN
Country of Wafer FabricationSINGAPORE
Additive Phase Jitter Typ RMS (fs)37.6
Core Voltage (V)3.3V, 2.5V
Family Name8T39
FunctionBuffer
Input Freq (MHz)1500
Input TypeCrystal, HCSL, LVDS, LVPECL, HSTL, LVCMOS
Inputs (#)3
Length (mm)5
MOQ260
Output Banks (#)2
Output Freq Range (MHz)1500
Output Skew (ps)81
Output TypeHCSL, LVDS, LVPECL
Output Voltage (V)2.5V, 3.3V
Outputs (#)4
Package Area (mm²)25
Pitch (mm)0.5
Pkg. Dimensions (mm)5.0 x 5.0 x 0.9
Pkg. TypeVFQFPN
Price (USD)$4.72733
Prog. InterfacePin select
Tape & ReelNo
Thickness (mm)0.9
Width (mm)5
已发布No

描述

The 8T39204 is a high-performance clock fanout buffer. The input clock can be selected from two differential inputs or one crystal input. The internal oscillator circuit is automatically disabled if the crystal input is not selected. The crystal pin can be driven by a single-ended clock. The selected signal is distributed to four differential outputs which can be configured as LVPECL, LVDS, or HCSL outputs. In addition, an LVCMOS output is provided. All outputs can be disabled into a high-impedance state. The device is designed for a signal fanout of high-frequency, low phase-noise clock and data signal. The outputs are at a defined level when inputs are open or tied to ground. It is designed to operate from a 3.3V or 2.5V core power supply, and either a 3.3V or 2.5V output operating supply.