特性
- High-performance clock RF-PLL with support for JESD204B
- Optimized for low phase noise: -150dBc/Hz (800kHz offset; 245.76MHz clock)
- Integrated phase noise of 63fs RMS typical (12k–20MHz).
- Dual-PLL architecture
- 1st-PLL stage with external VCXO for clock jitter attenuation
- 2nd-PLL with internal FemtoClock NG PLL: 2949.12MHz
- For 3932.16MHz: see 8V19N492-39
- For 3686.4MHz: see 8V19N491-36
- For 2457.6MHz: see 8V19N490-24 and 8V19N491-24
- For 1966.08MHz: see 8V19N490-19
- Five output channels with a total of 15 outputs
- Configurable integer clock frequency dividers
- Supported clock output frequencies include: 2949.12, 1474.56, 983.04, 491.52, 245.76, and 122.88 MHz
- Low-power LVPECL/LVDS outputs support configurable signal amplitude
- Phase delay circuits
- Redundant input clock architecture with two inputs and
- SYSREF generation modes include internal and external trigger mode for JESD204B
- Supply voltage: 3.3V
- Package: 10 × 10 mm, 88-VFQFPN
- Temperature range: -40°C to +105°C (Case)
描述
The 8V19N492 is a fully integrated FemtoClock® NG jitter attenuator and clock synthesizer designed as a high-performance clock solution for conditioning and frequency/phase management of wireless base station radio equipment boards. The device is optimized to deliver excellent phase noise performance as required in GSM, WCDMA, LTE, and LTE-A radio board implementations. The device supports JESD204B subclass 0 and 1 clocks.
A two-stage PLL architecture supports both jitter attenuation and frequency multiplication. The first stage PLL is the jitter attenuator and uses an external VCXO for best possible phase noise characteristics. The second stage PLL locks on the VCXO-PLL output signal and synthesizes the target frequency.
The device supports the clock generation of high-frequency clocks from the selected VCO and low-frequency synchronization signals (SYSREF). SYSREF signals are internally synchronized to the clock signals. Delay functions exist for achieving alignment and controlled phase delay between system reference and clock signals and to align/delay individual output signals. The two redundant inputs are monitored for activity. Four selectable clock switching modes are provided to handle clock input failure scenarios. Auto-lock, individually programmable output frequency dividers, and phase adjustment capabilities are added for flexibility. The 8V19N492 is ideal for driving converter circuits in wireless infrastructure, radar/imaging, and instrumentation/medical applications. The device is a member of the high-performance clock family from IDT.
For information regarding evaluation boards and material, please contact your local sales representative.
产品参数
| 属性 | 值 |
|---|---|
| Output Freq Range (MHz) | 18.432 - 2949.12 |
| Accepts Spread Spec Input | No |
| Supply Voltage (V) | 3.3 - 3.3 |
| Output Type | LVDS, LVPECL |
| Package Area (mm²) | 64 |
| Battery Backup | No |
| Battery Seal | No |
| CPU Supervisory Function POR | No |
| Crystal Frequency Trimming | No |
| Frequency Out Pin | No |
| Inputs (#) | 2 |
| Input Freq (MHz) | 1.92 - 2000 |
| DPLL Channels (#) | 0 |
| JESD204B/C Compliant | Yes |
| Frequency Plan | 2949.12 / Output_Divider |
| Adjustable Phase | Yes |
| Noise Floor (dBc/Hz) | -160 |
| Phase Noise Supports GSM | Yes |
| Synthesis Mode | Integer |
| Input Ref. Divider Resolution (bits) | 12 |
| Feedback Divider Resolution (bits) | 12 |
| Output Divider Resolution (bits) | 8 |
| Input Redundancy | Input Monitor, Auto-switch, Manual switch, Revertive and non-revertive switch, Holdover |
| Channels (#) | 1 |
| Additive Phase Jitter Typ RMS (fs) | 63.1 |
| Input Type | LVDS, LVPECL |
| Output Banks (#) | 5 |
| Core Voltage (V) | 3.3 |
| Output Voltage (V) | 3.3 |
| Product Category | JESD204B/C, Jitter Attenuators |
封装选项
| Pkg. Type | Pkg. Dimensions (mm) | Lead Count (#) | Pitch (mm) |
|---|---|---|---|
| VFQFPN | 10.0 x 10.0 x 0.9 | 88 | 0.4 |
