瑞萨电子 (Renesas Electronics Corporation)
搜索

9FGL839

过时

8-Output 3.3 V PCIe Gen 1-2-3 Clock Generator with Zo = 100 ohms

注意 - 建议使用以下设备作为替代品：
9FGL08 - 8-Output 3.3V PCIe Gen 1–6 Clock Generator

特性

  • Integrated terminations; save 32 resistors compared to standard HCSL outputs
  • LP-HCSL outputs; support separate VDDIO rail and 130mW typical power consumption
  • 8 OE# pins; hardware control of each output
  • 25MHz crystal input; exact synthesis
  • 100MHz operation; supports PCIe and SATA applications
  • VDDIO; allows outputs to run from lower voltage rail to save power
  • OE# pins have 1.5V high input threshold; direct interface to 1.8V to 3.3V systems
  • < 130mW power consumption (typical)
  • Cycle-to-Cycle jitter < 50ps
  • Output-to-Output skew < 100ps
  • PCIe Gen 2 phase jitter < 3.0ps RMS
  • PCIe Gen 3 phase jitter < 1.0ps RMS
  • PCIe Gen 3 SRnS clock phase jitter < 0.7ps RMS
查找应用特定型时钟的其他产品
9FGL839 Block Diagram
9FGL839 Pinout
9FGL839 Block Diagram
9FGL839 Pinout

描述

The 9FGL839 is an 8-output differential synthesizer for PCI Express Gen 1, Gen 2, and Gen 3 applications. It has integrated terminations providing direct connection to 100Ω transmission lines and saving 32 resistors compared to standard HCSL outputs. The 9FGL839 supports common, data, and Separate Reference no-Spread (SRnS) PCIe clock architectures.

当前筛选条件

加载中
加载中

This is the first video in our PCIe series. In this video, we define PCIe architectures, focusing on common and separate clock architectures. Watch the rest of the video series below where Ron will cover the impact of different timing architectures.

加载中 加载中