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替代产品

特性

• Phase-Lock Loop Clock Distribution for Synchronous DRAM applications
• Distributes one clock input to one bank of ten outputs
• External feedback (FBIN) pin is used to synchronize the outputs to the clock input signal
• Operates at 3.3V VDD
• tpd Phase Error at 133MHz: < ±150ps
• Jitter (peak-to-peak) at 133MHz: < ±75ps @ 133MHz
• Spread Spectrum Compatible
• Operating frequency 25MHz to 140MHz

描述

3.3V Phase lock loop, 1:10 Clock driver, zero delay buffer.  With the 74ALVCF162835A provides a complete solution for PC-100 and PC-133 SDRAM solutions. 

Part NumberStatusSamplesStockPackageLead Count (#)Temp. GradePb (Lead) FreeCarrier Type
CSP2510CPGObsoleteN/AOut of StockTSSOP24#CNoTube
CSP2510CPG8ObsoleteN/AOut of StockTSSOP24#CNoReel
CSP2510CPGGObsoleteN/AOut of StockTSSOP24#CYesTube
CSP2510CPGG8ObsoleteN/AOut of StockTSSOP24#CYesReel
CSP2510CPGIObsoleteN/AOut of StockTSSOP24#INoTube
CSP2510CPGI8ObsoleteN/AOut of StockTSSOP24#INoReel
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