特性
- 3 Micron Radiation Hardened CMOS SOS
- Total Dose 200K or 1 Mega-RAD(Si)
- Latch-Up Free Under Any Conditions
- Fanout (Over Temperature Range)
- Bus Driver Outputs - 15 LSTTL Loads
- Military Temperature Range: -55°C to +125°C
- Significant Power Reduction Compared to LSTTL ICs
- DC Operating Voltage Range: 4.5V to 5.5V
- LSTTL Input Compatibility
- VIL = 0.8V Max
- VIH = VCC/2 Min
- Input Current Levels Ii ≤ 5µA at VOL, VOH
描述
Support is limited to customers who have already adopted these products.
The Intersil HCS245MS is a Radiation Hardened Non-Inverting Octal Bidirectional Bus Transceiver, Three-State, intended for two-way asynchronous communication between data busses. The HCS245MS allows data transmission from the A bus to the B bus or from the B bus to the A bus. The logic level at the direction input (DIR) determines the data direction. The output enable input (OE) puts the I/O port in the high-impedance state when high. The HCS245MS utilizes advanced CMOS/SOS technology to achieve high-speed operation. This device is a member of radiation hardened, high-speed, CMOS/SOS Logic Family. The HCS245MS is supplied in a 20 lead Weld Seal Ceramic flatpack (K suffix) or a Weld Seal Ceramic Dual-In-Line Package (D suffix).
| Part Number | Status | Samples | Stock | Package | Lead Count (#) | Carrier Type | Moisture Sensitivity Level (MSL) | Pitch (mm) | Pkg. Dimensions (mm) | DLA SMD | Pb (Lead) Free | Pb Free Category | MOQ | Temp. Range (°C) | CAGE code |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| HCS245DMSR | Obsolete | N/A | Out of Stock | SBDIP | 20# | Tube | Not Applicable | 2.5mm | 25.4 x 7.5 x 2.41 | 5962-96797 | Exempt | Gold Plate over compliant Undercoat-e4 | 25 | -55 to +125°C | 34371 |
| HCS245KMSR | Obsolete | N/A | Out of Stock | CFP | 20# | Tray | Not Applicable | 1.3mm | 12.7 x 7.5 x 0.00 | 5962-96797 | Exempt | Gold Plate over compliant Undercoat-e4 | 25 | -55 to +125°C | 34371 |
- 应用说明英语PDF 224 KB an9654 1999年5月05日AI 生成的摘要: The document explains the reliability and failure mechanisms of semiconductor parts, focusing on life testing and wearout. It discusses how switching states cause transient current pulses and hot carrier injection, which only occur briefly during switching. Life testing at elevated temperatures accelerates aging to remove infant mortality failures, improving reliability. The failure rate follows a bathtub curve with infant mortality, useful life, and wearout phases, modeled by lognormal and exponential distributions. The Arrhenius equation relates failure rates at different temperatures. Burn-in and life tests reduce early failures without harming intrinsic reliability.
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- 应用说明英语PDF 224 KB an9654 1999年5月05日AI 生成的摘要: The document explains the reliability and failure mechanisms of semiconductor parts, focusing on life testing and wearout. It discusses how switching states cause transient current pulses and hot carrier injection, which only occur briefly during switching. Life testing at elevated temperatures accelerates aging to remove infant mortality failures, improving reliability. The failure rate follows a bathtub curve with infant mortality, useful life, and wearout phases, modeled by lognormal and exponential distributions. The Arrhenius equation relates failure rates at different temperatures. Burn-in and life tests reduce early failures without harming intrinsic reliability.
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