| CAD 模型: | View CAD Model |
| Pkg. Type: | SOICW |
| Pkg. Code: | MWV |
| Lead Count (#): | 28 |
| Pkg. Dimensions (mm): | 17.93 x 7.52 x 0.20 |
| Pitch (mm): | 1.27 |
| Pb (Lead) Free | No |
| ECCN (US) | EAR99 |
| HTS (US) | 8542.39.0030 |
| Moisture Sensitivity Level (MSL) |
| Lead Count (#) | 28 |
| Carrier Type | Tube |
| Pitch (mm) | 1.3 |
| Pkg. Dimensions (mm) | 17.9 x 7.5 x 0.20 |
| Pb (Lead) Free | No |
| Temp. Range (°C) | 0 to +70°C |
| Channels (#) | 1 |
| Conversion Rate (Max) (kSPS) | 60000 |
| Differential NonLinearity LSB | 1 |
| Digital Supply Voltage (V) | 3 - 3 |
| Input BW (MHz) | 250 |
| Input VIN ((VPP, differential)) | 1 |
| Integral NonLinearity LSB | 2 |
| Interface | CMOS |
| Length (mm) | 17.9 |
| MOQ | 78 |
| Pkg. Type | SOICW |
| Power Consumption (mW) | 260 |
| Qualification Level | Standard |
| Resolution (bits) | 10 |
| SFDR (dB) (dB) | 58.1 |
| SNR (dbFS) | 53.7 |
| Supply Voltage (V) | 5 - 5 |
| Thickness (mm) | 0.2 |
| Width (mm) | 7.5 |
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The HI5766 is a monolithic, 10-bit, analog-to-digital converter fabricated in a CMOS process. It is designed for high speed applications where wide bandwidth and low power consumption are essential. Its 60 MSPS speed is made possible by a fully differential pipelined architecture with an internal sample and hold. The HI5766 has excellent dynamic performance while consuming only 260mW power at 60 MSPS. Data output latches are provided which present valid data to the output bus with a latency of 7 clock cycles. It is pin-for-pin functionally compatible with the HI5702, HI5703 and the HI5746. For internal voltage reference, please refer to the HI5767 data sheet.