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VCSO Based Clock PLL

封装信息

Pkg. Type:CLCC
Pkg. Code:CG36
Lead Count (#):36
Pkg. Dimensions (mm):9.0 x 9.0 x 2.8
Pitch (mm):0.6

环境和出口类别

Pb (Lead) FreeYes
ECCN (US)EAR99
HTS (US)8542.39.0090
Moisture Sensitivity Level (MSL)1

产品属性

Pkg. TypeCLCC
Lead Count (#)36
Pb (Lead) FreeYes
Carrier TypeReel
Abs. Pull Range Min. (± PPM)50
Core Voltage (V)3.3
Feedback InputNo
Input Freq (MHz)15 - 700
Input TypeLVCMOS, LVPECL, LVDS
Inputs (#)2
Length (mm)9
MOQ500
Moisture Sensitivity Level (MSL)1
Output Banks (#)2
Output Freq Range (MHz)77.76 - 77.76, 155.52 - 155.52
Output TypeLVPECL
Output Voltage (V)3.3
Outputs (#)2
Package Area (mm²)81
Pb Free Categorye4 Au
Phase Jitter Max RMS (ps)0.6
Phase Jitter Typ RMS (ps)0.4
Pitch (mm)0.6
Pkg. Dimensions (mm)9.0 x 9.0 x 2.8
Prog. ClockNo
Qty. per Carrier (#)0
Qty. per Reel (#)500
Requires Terms and ConditionsDoes not require acceptance of Terms and Conditions
Tape & ReelYes
Temp. Range (°C)-40 to 85°C
Thickness (mm)2.8
Width (mm)9

描述

The M1020/21 is a VCSO (Voltage Controlled SAW Oscillator) based clock jitter attenuator PLL designed for clock jitter attenuation and frequency translation. The device is ideal for generating the transmit reference clock for optical network systems supporting up to 2.5Gb data rates. It can serve to jitter attenuate a stratum reference clock or a recovered clock in loop timing mode. The M1020/21 module includes a proprietary SAW (surface acoustic wave) delay line as part of the VCSO. This results in a high frequency, high-Q, low phase noise oscillator that assures low intrinsic output jitter.