封装信息
| Pkg. Type: | CLCC |
| Pkg. Code: | CG36 |
| Lead Count (#): | 36 |
| Pkg. Dimensions (mm): | 9.0 x 9.0 x 2.8 |
| Pitch (mm): | 0.6 |
环境和出口类别
| Pb (Lead) Free | Yes |
| Moisture Sensitivity Level (MSL) | 1 |
| ECCN (US) | |
| HTS (US) |
产品属性
| Pkg. Type | CLCC |
| Lead Count (#) | 36 |
| Pb (Lead) Free | Yes |
| Carrier Type | Tube |
| Common Input Freq (MHz) | 625MHz, 644.53MHz |
| Core Voltage (V) | 3.3 |
| Diff. Input Signaling | 3.3 |
| Diff. Output Signaling | 3.3 |
| Divider Value | 1, 4, 8, 32 |
| Feedback Divider | 1 - 1, 4 - 4, 8 - 8, 32 - 32 |
| Function | Frequency Translation PLL for GbE with FEC (64B/66B) |
| I/O Voltage (V) | 3.3 - 3.3 |
| Input Freq (MHz) | 10 - 700 |
| Input Type | LVPECL |
| Inputs (#) | 2 |
| Length (mm) | 9 |
| M/R Look-Up Table | Yes |
| MOQ | 57 |
| Moisture Sensitivity Level (MSL) | 1 |
| Operating Freq | 644.531 |
| Output Banks (#) | 1 |
| Output Freq Range (MHz) | 15 - 700 |
| Output Signaling | LVPECL |
| Output Type | LVPECL |
| Output Voltage (V) | 3.3 |
| Outputs (#) | 2 |
| Package Area (mm²) | 81 |
| Pb Free Category | e4 Au |
| Phase Jitter Max RMS (ps) | 0.5 |
| Phase Jitter Typ RMS (ps) | 0.25 |
| Pitch (mm) | 0.6 |
| Pkg. Dimensions (mm) | 9.0 x 9.0 x 2.8 |
| Qty. per Carrier (#) | 54 |
| Qty. per Reel (#) | 0 |
| Requires Terms and Conditions | Does not require acceptance of Terms and Conditions |
| Supply Voltage (V) | 3.3 - 3.3 |
| Tape & Reel | No |
| Temp. Range (°C) | 0 to 70°C |
| Thickness (mm) | 2.8 |
| Width (mm) | 9 |
有关 M2053 的资源
描述
The M2053 is a VCSO (Voltage Controlled SAW Oscillator) based clock PLL designed for FEC clock ratio translation in 10Gb optical systems such as 10GbE 64b/66b. It supports both mapping and de-mapping of 64b/66b encoding and FEC (Forward Error Correction) clock multiplication ratios. The ratios are pin-selected from pre-programming look-up tables.
