概览
描述
The SLG46121 provides a small, low-power component for commonly used mixed-signal functions. The user creates their circuit design by programming the one-time programmable (OTP) non-volatile memory (NVM) to configure the interconnect logic, the I/O pins, and the macrocells of the SLG46121. This highly versatile device allows for a wide variety of mixed-signal functions to be designed within a very small, low-power single integrated circuit. The additional power supply (VDD2) on the SLG46121 provides the ability to interface two independent voltage domains within the same design. Users can configure pins, dedicated to each power supply, as inputs, outputs, or both (controlled dynamically by internal logic) to both VDD and VDD2 voltage domains. Using the available macrocells, designers can implement mixed-signal functions bridging both domains or simply pass through level translation in both High to Low and Low to High directions.
特性
- Logic and Mixed Signal Circuits
- Highly Versatile Macrocells
- 1.8V (±5%) to 5V (±10%) VDD
- 1.8V (±5%) to 5V (±10%) VDD2 (VDD2 ≤ VDD)
- Operating Temperature Range: -40 °C to 85 °C
- RoHS Compliant/Halogen-Free
- Pb-Free
- Macrocells Overview
- Two Analog Comparators (ACMP)
- Voltage References (Vref)
- Five Combinatorial Look-Up Tables (LUTs)
- One 2-bit LUT
- Four 3-bit LUTs
- Twelve Combination Function Macrocell
- Four Selectable DFF/Latch or 2-bit LUTs
- Four Selectable DFF/Latch or 3-bit LUTs
- One Selectable Pipe Delay or 3-bit LUT
- Pipe Delay - 8 Stage/2 Output
- One Bandgap
- Two Selectable Counter/Delay or 4-bit LUT
- One Programmable Delay/Deglitch Filter
- One Selectable Pipe Delay or 3-bit LUT
- Pipe Delay - 8 Stage/2 Output
- Two Counter/Delay Generators (CNT/DLY)
- One 8-bit Counter/Delay
- One 14-bit Counter/Delay with External Clock/Reset
- Eight D Flip-Flop/Latches (DFF) (Part of Combination Function Macrocell)
- Additional Logic Function - 1 Inverter
- Pipe Delay - 8 Stage/2 Output (Part of Combination Function Macrocell)
- RC Oscillator (RC OSC)
- Power-On Reset (POR)
