特性
- JEDEC Center Power/GND pinout for reduced noise
- Equal access and cycle times
- Commercial and Industrial: 10/12/15ns
- Single 3.3V power supply
- One Chip Select plus one Output Enable pin
- Bidirectional data inputs and outputs directly
- TTL-compatible
- Low power consumption via chip deselect
- Available in 36-pin, 400 mil plastic SOJ and 44-pin, 400 mil TSOP packages
描述
The 71V424 3.3V CMOS SRAM is organized as 512K x 8. All bidirectional inputs and outputs of the 71V424 are TTL-compatible and operation is from a single 3.3V supply. Fully static asynchronous circuitry is used, requiring no clocks or refresh for operation.
产品参数
| 属性 | 值 |
|---|---|
| Density (Kb) | 4096 |
| Bus Width (bits) | 8 |
| Core Voltage (V) | 3.3 |
| Organization | 512K x 8 |
| I/O Voltage (V) | - |
| Access Time (ns) | 10, 12, 15 |
| Temp. Range (°C) | -40 to 85°C, 0 to 70°C |
| Architecture | Asynchronous |
封装选项
| Pkg. Type | Pkg. Dimensions (mm) | Lead Count (#) | Pitch (mm) |
|---|---|---|---|
| TSOP | 18.41 x 10.16 x 1.0 | 44 | 0.8 |