封装信息
| Lead Count (#) | 100 |
| Pkg. Code | PKG100 |
| Pitch (mm) | 0.65 |
| Pkg. Type | TQFP |
| Pkg. Dimensions (mm) | 20.0 x 14.0 x 1.4 |
环境和出口类别
| Pb (Lead) Free | Yes |
| ECCN (US) | NLR |
| HTS (US) | 8542320041 |
| Moisture Sensitivity Level (MSL) | 3 |
产品属性
| Lead Count (#) | 100 |
| Pb (Lead) Free | Yes |
| Carrier Type | Tray |
| Price (USD) | 1ku | 6.02495 |
| Architecture | Synch Burst |
| Bus Width (bits) | 32 |
| Core Voltage (V) | 3.3 |
| Density (Kb) | 2048 |
| I/O Voltage (V) | 3.3 - 3.3 |
| Length (mm) | 20.0 |
| MOQ | 576 |
| Moisture Sensitivity Level (MSL) | 3 |
| Organization | 64K x 32 |
| Output Type | Pipelined |
| Package Area (mm²) | 280.0 |
| Pb Free Category | e3 Sn |
| Pitch (mm) | 0.65 |
| Pkg. Dimensions (mm) | 20.0 x 14.0 x 1.4 |
| Pkg. Type | TQFP |
| Qty. per Carrier (#) | 72 |
| Qty. per Reel (#) | 0 |
| Requires Terms and Conditions | Does not require acceptance of Terms and Conditions |
| Tape & Reel | No |
| Temp. Range | -40 to 85°C |
| Thickness (mm) | 1.4 |
| Width (mm) | 14.0 |
描述
The 71V632 3.3V CMOS SRAM is organized as 64K x 32. The pipelined burst architecture provides cost-effective 3-1-1-1 secondary cache performance for processors up to 117MHz. The 71V632 SRAM contains write, data, address, and control registers. The burst mode feature offers the highest level of performance to the system designer, as it can provide four cycles of data for a single address presented to the SRAM.